- Aurélie Saulquin, CRIStAL, Centre de Recherche en Informatique, Signals et Automatique de Lille, UMR 9189, <aurelie.saulquin@univ-lille.fr>, Design, Coding, Architectur
- Aurélie Saulquin, CRIStAL, Centre de Recherche en Informatique, Signals et Automatique de Lille, UMR 9189, <aurelie.saulquin@univ-lille.fr>, Design, Coding, Architecture
- Mazdak Fatahi, CRIStAL, Centre de Recherche en Informatique, Signals et Automatique de Lille, UMR 9189, <mazdak.fatahi@univ-lille.fr>, Network trainning
**ModNEF**: **Mod**ular **N**euromorphic **E**mulator for **F**PGA, is a digital neuromorphic hardware architecture designed for low-power, edge-based artificial intelligence inference using Spiking Neural Networks. Developed in VHDL, ModNEF has been successfully implemented and tested on the Arty-Z7 20 FPGA board.
In addition to the FPGA architecture, we offer a Python library that simplifies the process of training and deploying models onto FPGA hardware and a Rust UART driver to transmit inputs spikes to FPGAwith UART communication protocol.
## Repository Overview
-**Examples** (not up to date): Contains multiple examples demonstrating how to use ModNEF tools.
-**LICENSES**: Includes license files for the repository.
-**ModNEF_Debugger**: Provides simulation-only ModNEF modules for running Vivado simulations.
-**ModNEF_Sources**: Contains the VHDL files for the ModNEF architecture.
-**modneflib**: Python library for ModNEF, including:
-**modnef_driver**: Python drivers for FPGA interaction.
-**modnef_torch**: Additional tools for SNNTorch tailored for ModNEF.
-**quantizer**: Tools for quantization.
-**Network Papers** (not up to date): Features various models presented in our research papers.
-**rust_driver**: Rust-based FPGA driver.
## Overview
## Dependencies
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@@ -53,36 +68,37 @@ Rust driver must be compiled first to correctly build ModNEF Python library.
- Install the library : `pip install .`
-*optional* Try to open modnef in python consol by typing : `from modnef import *`
### Check installation
The `examples/check_installation` project is a simple project which integrate all ModNEF features in therms of tools and vhdl script.
## Running Examples and Network Papers
The next step explain how
#### Create project
1. Create vivado project
2. From vivado add sources and import fpga_sources directory to you project
3. Import Your top level and memory files generated by ModNEF architecture builder.
<spanstyle="color:red">**Note**: The networks presented in the papers were created with a previous version of ModNEF and may no longer be supported.</span>
To avoid file accumulation, only the binary networks generated by SnnTorch are shared. To use the provided networks, follow these steps:
## Run examples and network paper
### Examples
To avoid the accumulation of files, only the binary network generated by SnnTorch is shared. To use the proposed network please follow the followings steps:
ModNEF offers two examples:
### Example
ModNEF propose two differents example. The first example [NetworkInference](./examples/network_example) is a good introduction to ModNEF architecture builder and ModNEF drivers. The others example is[Debugger](./examples/debugger_example/) that introduce ModNEF debugging and simulation tools.
1.**Network Inference**: Located in [NetworkInference](./examples/network_example), this example serves as an introduction to the ModNEF architecture builder and drivers.
2.**Debugger**: Found in[Debugger](./examples/debugger_example/), this example introduces ModNEF's debugging and simulation tools.
### Network Papers
We provides all presented network in the paper into [NetworkPaper](./NetworkPaper/) directory. To run these network please follows the following steps:
1. Open a terminal is the subdirectory of network you want to run
2. Run the command `python3 ./load_network.py` that will load the binary network and generate synaptic weight file.
3. Open the `arch_build.py` file and modify the constant value (starting by underscore) to correspond to your value.
4. Run `python3 ./arch_build.py` command that will generate VHDL architecture file and memory file.
5. Add VHDL and memory file to your vivado project.
6. Generate the bitstream and put the circuit to your FPGA.
7. In `inference.py` file, change the dataset path and the path to the USB board file. If you want to save the inference result, set the `_SAVE` flag to true and modify the file name of output file.
8. Run `./inference.py`. The administrator access can be necessary.
All networks presented in the papers are available in the [NetworkPaper](./NetworkPaper/) directory. To run these networks, follow these steps:
1. Open a terminal in the subdirectory of the network you wish to run.
2. Execute the command `python3 ./load_network.py` to load the binary network and generate the synaptic weight file.
3. Open the `arch_build.py` file and modify the constant values (prefixed with an underscore) to match your settings.
4. Run the command `python3 ./arch_build.py` to generate the VHDL architecture file and memory file.
5. Add the VHDL and memory files to your Vivado project.
6. Generate the bitstream and load it onto your FPGA.
7. In the `inference.py` file, update the dataset path and the path to the USB board file. If you wish to save the inference results, set the `_SAVE` flag to `True` and modify the output file name.
8. Run `python3 ./inference.py`. Administrator access may be required.
## Version note
Version : 2.1
Version note : add Quantization Aware Training algorithms.
## License
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@@ -90,3 +106,18 @@ The FPGA source of ModNEF is licensed under the [CERN Open Hardware Licence Vers
## Cite US
```
@article{saulquin_modnef_2025,
title = {{ModNEF} : An Open Source Modular Neuromorphic Emulator for {FPGA} for Low-Power In-Edge Artificial Intelligence},
rights = {Creative Commons Attribution-{ShareAlike} 4.0 International License},
"description":"ModNEF is a modular neuromorphic FPGA architecture generator for low-power in edge artificial intelligence based on spiking neural network.",
"funder":{
"type":"Organization",
"name":"University of Lille, Conseil régional Haut de France"
