diff --git a/AUTHORS b/AUTHORS index 43d49244cd94d1ceb4c8393329c630b760212058..34bdc16cb2bc8ab52ec6fa478761c6d8da40dcf7 100644 --- a/AUTHORS +++ b/AUTHORS @@ -1,7 +1,7 @@ # Authors # Constributors -- Aurélie Saulquin, CRIStAL, Centre de Recherche en Informatique, Signals et Automatique de Lille, UMR 9189, <aurelie.saulquin@univ-lille.fr>, Design, Coding, Architectur +- Aurélie Saulquin, CRIStAL, Centre de Recherche en Informatique, Signals et Automatique de Lille, UMR 9189, <aurelie.saulquin@univ-lille.fr>, Design, Coding, Architecture - Mazdak Fatahi, CRIStAL, Centre de Recherche en Informatique, Signals et Automatique de Lille, UMR 9189, <mazdak.fatahi@univ-lille.fr>, Network trainning diff --git a/README.md b/README.md index 9ce8d51c28e435928c706f94a3401f4b0c402236..5b2aa512db2be24ddaa96b562ca65a20bce75b73 100644 --- a/README.md +++ b/README.md @@ -1,8 +1,23 @@ # ModNEF : MODular Neuromorphic Emulator for Fpga -## Introduction +**ModNEF**: **Mod**ular **N**euromorphic **E**mulator for **F**PGA, is a digital neuromorphic hardware architecture designed for low-power, edge-based artificial intelligence inference using Spiking Neural Networks. Developed in VHDL, ModNEF has been successfully implemented and tested on the Arty-Z7 20 FPGA board. + +In addition to the FPGA architecture, we offer a Python library that simplifies the process of training and deploying models onto FPGA hardware and a Rust UART driver to transmit inputs spikes to FPGAwith UART communication protocol. + +## Repository Overview + +- **Examples** (not up to date): Contains multiple examples demonstrating how to use ModNEF tools. +- **LICENSES**: Includes license files for the repository. +- **ModNEF_Debugger**: Provides simulation-only ModNEF modules for running Vivado simulations. +- **ModNEF_Sources**: Contains the VHDL files for the ModNEF architecture. +- **modneflib**: Python library for ModNEF, including: + - **arch_builder**: Generates ModNEF VHDL architectures. + - **modnef_driver**: Python drivers for FPGA interaction. + - **modnef_torch**: Additional tools for SNNTorch tailored for ModNEF. + - **quantizer**: Tools for quantization. +- **Network Papers** (not up to date): Features various models presented in our research papers. +- **rust_driver**: Rust-based FPGA driver. -## Overview ## Dependencies @@ -53,36 +68,37 @@ Rust driver must be compiled first to correctly build ModNEF Python library. - Install the library : `pip install .` - *optional* Try to open modnef in python consol by typing : `from modnef import *` -### Check installation -The `examples/check_installation` project is a simple project which integrate all ModNEF features in therms of tools and vhdl script. +## Running Examples and Network Papers -The next step explain how -#### Create project -1. Create vivado project -2. From vivado add sources and import fpga_sources directory to you project -3. Import Your top level and memory files generated by ModNEF architecture builder. +<span style="color:red">**Note**: The networks presented in the papers were created with a previous version of ModNEF and may no longer be supported.</span> +To avoid file accumulation, only the binary networks generated by SnnTorch are shared. To use the provided networks, follow these steps: -## Run examples and network paper +### Examples -To avoid the accumulation of files, only the binary network generated by SnnTorch is shared. To use the proposed network please follow the followings steps: +ModNEF offers two examples: -### Example -ModNEF propose two differents example. The first example [NetworkInference](./examples/network_example) is a good introduction to ModNEF architecture builder and ModNEF drivers. The others example is [Debugger](./examples/debugger_example/) that introduce ModNEF debugging and simulation tools. +1. **Network Inference**: Located in [NetworkInference](./examples/network_example), this example serves as an introduction to the ModNEF architecture builder and drivers. +2. **Debugger**: Found in [Debugger](./examples/debugger_example/), this example introduces ModNEF's debugging and simulation tools. ### Network Papers -We provides all presented network in the paper into [NetworkPaper](./NetworkPaper/) directory. To run these network please follows the following steps: -1. Open a terminal is the subdirectory of network you want to run -2. Run the command `python3 ./load_network.py` that will load the binary network and generate synaptic weight file. -3. Open the `arch_build.py` file and modify the constant value (starting by underscore) to correspond to your value. -4. Run `python3 ./arch_build.py` command that will generate VHDL architecture file and memory file. -5. Add VHDL and memory file to your vivado project. -6. Generate the bitstream and put the circuit to your FPGA. -7. In `inference.py` file, change the dataset path and the path to the USB board file. If you want to save the inference result, set the `_SAVE` flag to true and modify the file name of output file. -8. Run `./inference.py`. The administrator access can be necessary. +All networks presented in the papers are available in the [NetworkPaper](./NetworkPaper/) directory. To run these networks, follow these steps: + +1. Open a terminal in the subdirectory of the network you wish to run. +2. Execute the command `python3 ./load_network.py` to load the binary network and generate the synaptic weight file. +3. Open the `arch_build.py` file and modify the constant values (prefixed with an underscore) to match your settings. +4. Run the command `python3 ./arch_build.py` to generate the VHDL architecture file and memory file. +5. Add the VHDL and memory files to your Vivado project. +6. Generate the bitstream and load it onto your FPGA. +7. In the `inference.py` file, update the dataset path and the path to the USB board file. If you wish to save the inference results, set the `_SAVE` flag to `True` and modify the output file name. +8. Run `python3 ./inference.py`. Administrator access may be required. + +## Version note +Version : 2.1 +Version note : add Quantization Aware Training algorithms. ## License @@ -90,3 +106,18 @@ The FPGA source of ModNEF is licensed under the [CERN Open Hardware Licence Vers ## Cite US +``` +@article{saulquin_modnef_2025, + title = {{ModNEF} : An Open Source Modular Neuromorphic Emulator for {FPGA} for Low-Power In-Edge Artificial Intelligence}, + rights = {Creative Commons Attribution-{ShareAlike} 4.0 International License}, + issn = {1544-3566}, + url = {https://dl.acm.org/doi/10.1145/3730581}, + doi = {10.1145/3730581}, + shorttitle = {{ModNEF}}, + journaltitle = {{ACM} Trans. Archit. Code Optim.}, + author = {Saulquin, Aurélie and Fatahi, Mazdak and Boulet, Pierre and Meftali, Samy}, + urldate = {2025-04-17}, + date = {2025-04-16}, + note = {Just Accepted}, +} +``` \ No newline at end of file diff --git a/codemeta.json b/codemeta.json index 7d77ad503bed0bf4704c6fb1e134265e01d7ae8f..35bdd4fbfb20d699533368b7349c13377be55b63 100644 --- a/codemeta.json +++ b/codemeta.json @@ -1 +1,82 @@ -"https://codemeta.github.io/codemeta-generator/" \ No newline at end of file +{ + "@context": "https://doi.org/10.5063/schema/codemeta-2.0", + "type": "SoftwareSourceCode", + "applicationCategory": "Artificial Intelligence", + "author": [ + { + "id": "https://orcid.org/0009-0002-4065-0553", + "type": "Person", + "affiliation": { + "type": "Organization", + "name": "UMR 9189 CRIStAL" + }, + "email": "aurelie.saulquin@univ-lille.fr", + "familyName": "Saulquin", + "givenName": "Aurélie" + }, + { + "id": "https://orcid.org/0000-0001-5881-3555", + "type": "Person", + "affiliation": { + "type": "Organization", + "name": "UMR 9189 CRIStAL" + }, + "email": "mazdak.fatahi@univ-lille.fr", + "familyName": "Fatahi", + "givenName": "Mazdak" + }, + { + "id": "https://orcid.org/0000-0002-0373-4478", + "type": "Person", + "affiliation": { + "type": "Organization", + "name": "UMR 9189 CRIStAL" + }, + "email": "pierre.boulet@univ-lille.fr", + "familyName": "Boulet", + "givenName": "Pierre" + }, + { + "id": "https://orcid.org/0000-0002-0589-3042", + "type": "Person", + "affiliation": { + "type": "Organization", + "name": "UMR 9189 CRIStAL" + }, + "email": "samy.meftali@univ-lille.fr", + "familyName": "Meftali", + "givenName": "Samy" + } + ], + "codeRepository": "https://gitlab.univ-lille.fr/bioinsp/ModNEF", + "dateCreated": "2023-05-24", + "dateModified": "2025-04-17", + "datePublished": "2024-10-20", + "description": "ModNEF is a modular neuromorphic FPGA architecture generator for low-power in edge artificial intelligence based on spiking neural network.", + "funder": { + "type": "Organization", + "name": "University of Lille, Conseil régional Haut de France" + }, + "keywords": [ + "Spiking Neural Network", + "FPGA", + "Neuromorphic Accelerator", + "Edge Computing", + "Articifial Intelligence", + "Parallel Architecture" + ], + "license": [ + "https://spdx.org/licenses/GPL-3.0+", + "https://spdx.org/licenses/CERN-OHL-S-2.0.html" + ], + "name": "ModNEF", + "operatingSystem": "Linux", + "programmingLanguage": [ + "VHDL", + "Python", + "Rust" + ], + "schema:releaseNotes": "Add Quantization Aware Training", + "version": "2.1.0", + "referencePublication": "http://dx.doi.org/10.1145/3730581." +} \ No newline at end of file