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SpiNNaker

Last edited by Hammouda Elbez

SpiNNaker is a biologically inspired, massively parallel computing system optimized for modeling and simulating large-scale real-time networks. In the neuromorphic platform, we have the SpiNN-5 (SpiNNaker 103) board 1 2, which consists of 48 SpiNNaker chips. Each chip contains 18 ARM cores with a 32 kB ITCM (instruction tightly coupled memory) and a 64 kB DTCM (data tightly coupled memory) per core. Moreover, a 128 MB SDRAM is shared between the 18 cores. To imitate the high connectivity of the brain, the cores are interconnected by an asynchronous Network-on-Chip (NoC) through a multicast packet-routing mechanism. In addition, SpiNN-5 uses three Xilinx Spartan-6 FPGAs for high-speed serial links.

A 100 MB Ethernet controller handles the connection between the SpiNNaker board and the computer. We use it to load data to the SpiNNaker memory to perform a real-time simulation. Furthermore, the sPyNNaker 3 is a software package that defines models in PyNN script 4 and translates models into a suitable form for SpiNNaker.

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Spinn-5

Useful Scripts

To facilitate the use of the board, a few scripts are available:

In addition, examples of use are also available here:

Official Documentation

Software for SpiNNaker:
https://spinnakermanchester.github.io/

PyNN: A Python package for simulator-independent specification of neuronal network models:
https://neuralensemble.org/PyNN/

References

  1. Painkras, E., Plana, L. A., Garside, J., Temple, S., Galluppi, F., Patterson, C., et al. (2013). Spinnaker: A 1-w 18-core system-on-chip for massively-parallel neural network simulation. IEEE Journal of Solid-State Circuits 48, 1943–1953 ↩

  2. Furber, S. B., Lester, D. R., Plana, L. A., Garside, J. D., Painkras, E., Temple, S., et al. (2012). Overview of the spinnaker system architecture. IEEE transactions on computers 62, 2454–2467 ↩

  3. Rhodes, O., Bogdan, P. A., Brenninkmeijer, C., Davidson, S., Fellows, D., Gait, A., et al. (2018). spynnaker: a software package for running pynn simulations on spinnaker. Frontiers in neuroscience 12, 816 ↩

  4. Davison, A. P., Brüderle, D., Eppler, J. M., Kremkow, J., Muller, E., Pecevski, D., et al. (2009). Pynn: a common interface for neuronal network simulators. Frontiers in neuroinformatics 2, 11 ↩

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