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Commit 020909b7 authored by ahoni's avatar ahoni
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add clamp test

parent 825a6a46
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with 108 additions and 125 deletions
......@@ -29,11 +29,10 @@ entity beta_lif is
v_threshold : std_logic_vector;
beta : std_logic_vector;
reset : string := "zero";
compute_fp : integer := 8;
fixed_point : integer := 1;
weight_size : integer := 2;
weight_signed : boolean := false;
weight_fp : integer := 1
weight_signed : boolean := false
);
Port (
i_clk : in std_logic;
......@@ -74,10 +73,6 @@ architecture Behavioral of beta_lif is
signal v_debug : std_logic_vector(variable_size-1 downto 0) := (others=>'0');
signal v_mult_debug : std_logic_vector(variable_size*2-1 downto 0) := (others=>'0');
-- weight signals
constant weight_offset_size : integer := compute_fp-weight_fp;
constant weight_offset : std_logic_vector(weight_offset_size-1 downto 0) := (others=>'0');
begin
o_spike <= spike;
......@@ -85,8 +80,8 @@ begin
process(i_clk, i_inc_I, i_calc, i_en, i_reset)
variable V_mult : std_logic_vector(variable_size*2-1 downto 0) := (others => '0');
variable V_buff : std_logic_vector(variable_size-1 downto 0);
variable I : std_logic_vector(weight_size+weight_offset_size-1 downto 0);
variable I_rec : std_logic_vector(weight_size+weight_offset_size-1 downto 0);
variable I : std_logic_vector(weight_size-1 downto 0);
variable I_rec : std_logic_vector(weight_size-1 downto 0);
begin
if rising_edge(i_clk) then
if i_reset = '1' then
......@@ -109,13 +104,13 @@ begin
if i_inc_I = '1' or i_inc_I_rec = '1' then
if i_inc_I = '1' then
I := std_logic_vector(signed(i_w&weight_offset));
I := std_logic_vector(signed(i_w));
else
I := (others=>'0');
end if;
if i_inc_I_rec = '1' then
I_rec := std_logic_vector(signed(i_w_rec&weight_offset));
I_rec := std_logic_vector(signed(i_w_rec));
else
I_rec := (others=>'0');
end if;
......@@ -126,7 +121,7 @@ begin
case state is
when multiplication =>
V_mult := std_logic_vector(signed(V) * signed(beta));
V_buff := V_mult(compute_fp + variable_size-1 downto compute_fp);
V_buff := V_mult(fixed_point + variable_size-1 downto fixed_point);
if signed(V_buff) >= signed(v_threshold) then
spike <= '1';
......@@ -155,18 +150,18 @@ begin
else -- unsigned
if i_inc_I = '1' or i_inc_I_rec = '1' then
if i_inc_I = '1' and i_inc_I_rec = '0' then
V <= std_logic_vector(unsigned(V) + unsigned(i_w&weight_offset));
V <= std_logic_vector(unsigned(V) + unsigned(i_w));
elsif i_inc_I = '0' and i_inc_I_rec = '1' then
V <= std_logic_vector(unsigned(V) + unsigned(i_w_rec&weight_offset));
V <= std_logic_vector(unsigned(V) + unsigned(i_w_rec));
else
V <= std_logic_vector(unsigned(V) + unsigned(i_w&weight_offset) + unsigned(i_w_rec&weight_offset));
V <= std_logic_vector(unsigned(V) + unsigned(i_w) + unsigned(i_w_rec));
end if;
elsif calc = '1' then
case state is
when multiplication =>
V_mult := std_logic_vector(unsigned(V) * unsigned(beta));
V_buff := V_mult(compute_fp + variable_size-1 downto compute_fp);
V_buff := V_mult(fixed_point + variable_size-1 downto fixed_point);
if unsigned(V_buff) >= unsigned(v_threshold) then
spike <= '1';
......
......@@ -32,11 +32,10 @@ entity BLif_Parallel is
v_threshold : std_logic_vector;
beta : std_logic_vector;
reset : string := "zero";
compute_fp : integer := 8;
fixed_point : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false;
weight_fp : integer := 1;
mem_init_file : string := "none"
);
......@@ -105,11 +104,10 @@ architecture Behavioral of BLif_Parallel is
v_threshold : std_logic_vector;
beta : std_logic_vector;
reset : string := "zero";
compute_fp : integer := 8;
fixed_point : integer := 1;
weight_size : integer := 2;
weight_signed : boolean := false;
weight_fp : integer := 1
weight_signed : boolean := false
);
Port (
i_clk : in std_logic;
......@@ -326,10 +324,9 @@ begin
v_threshold => v_threshold,
beta => beta,
reset => reset,
compute_fp => compute_fp,
fixed_point => fixed_point,
weight_size => weight_size,
weight_signed => weight_signed,
weight_fp => weight_fp
weight_signed => weight_signed
) port map(
i_clk => i_clk,
i_en => '1',
......
......@@ -37,11 +37,10 @@ entity BLif_Sequential is
v_threshold : std_logic_vector;
beta : std_logic_vector;
reset : string := "zero";
compute_fp : integer := 8;
fixed_point : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false;
weight_fp : integer := 1;
mem_init_file : string := "none"
);
......@@ -91,10 +90,6 @@ architecture Behavioral of BLif_Sequential is
type transmission_state_t is (idle, request, accept, get_voltage, emulate, set_voltage, emulate_finish);
type reception_state_t is (idle, request, wait_data, get_data, update_current);
-- weight ofsset definition
constant weight_offset_size : integer := compute_fp-weight_fp;
constant weight_offset : std_logic_vector(weight_offset_size-1 downto 0) := (others=>'0');
-- ram signals
signal data_read : std_logic_vector((output_neuron*weight_size)-1 downto 0);
signal ram_en : std_logic;
......@@ -197,9 +192,9 @@ begin
for I in 0 to output_neuron-1 loop
w := data_read((I*weight_size)+weight_size-1 downto I*weight_size);
if weight_signed then
current_array(I) <= std_logic_vector(signed(current_array(I)) + signed((unsigned(w)&unsigned(weight_offset))));
current_array(I) <= std_logic_vector(signed(current_array(I)) + signed(w));
else
current_array(I) <= std_logic_vector(unsigned(current_array(I)) + unsigned((unsigned(w)&unsigned(weight_offset))));
current_array(I) <= std_logic_vector(unsigned(current_array(I)) + unsigned(w));
end if;
end loop;
end if;
......@@ -279,10 +274,10 @@ begin
when emulate => -- emulation state
if weight_signed then
v_mult := std_logic_vector(signed(v)*signed(beta));
v_next <= v_mult(compute_fp+variable_size-1 downto compute_fp);
v_next <= v_mult(fixed_point+variable_size-1 downto fixed_point);
else
v_mult := std_logic_vector(unsigned(v)*unsigned(beta));
v_next <= v_mult(compute_fp+variable_size-1 downto compute_fp);
v_next <= v_mult(fixed_point+variable_size-1 downto fixed_point);
end if;
o_aer <= std_logic_vector(to_unsigned(counter, log_b(output_neuron, 2)));
transmission_state <= set_voltage;
......
......@@ -32,11 +32,10 @@ entity RBLIF_Parallel is
v_threshold : std_logic_vector;
beta : std_logic_vector;
reset : string := "zero";
compute_fp : integer := 8;
fixed_point : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false;
weight_fp : integer := 1;
mem_init_file : string := "none";
mem_init_file_rec : string := ""
......@@ -127,11 +126,10 @@ architecture Behavioral of RBLIF_Parallel is
v_threshold : std_logic_vector;
beta : std_logic_vector;
reset : string := "zero";
compute_fp : integer := 8;
fixed_point : integer := 8;
weight_size : integer := 2;
weight_signed : boolean := false;
weight_fp : integer := 1
weight_signed : boolean := false
);
Port (
i_clk : in std_logic;
......@@ -383,10 +381,9 @@ begin
v_threshold => v_threshold,
beta => beta,
reset => reset,
compute_fp => compute_fp,
fixed_point => fixed_point,
weight_size => weight_size,
weight_signed => weight_signed,
weight_fp => weight_fp
weight_signed => weight_signed
) port map(
i_clk=>i_clk,
i_en=>neuron_en,
......
......@@ -37,11 +37,10 @@ entity RBLif_Sequential is
v_threshold : std_logic_vector;
beta : std_logic_vector;
reset : string := "zero";
compute_fp : integer := 8;
fixed_point : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false; -- w_unsigned or w_signed
weight_fp : integer := 1;
weight_signed : boolean := false;
mem_init_file : string := "none";
mem_init_file_rec : string := ""
......@@ -92,10 +91,6 @@ architecture Behavioral of RBLif_Sequential is
type reception_state_t is (idle, request, wait_data, get_data, update_current);
type transmission_state_t is (idle, request, accept, get_voltage, emulate, set_voltage, emulate_finish);
-- weight offset definition
constant weight_offset_size : integer := compute_fp-weight_fp;
constant weight_offset : std_logic_vector(weight_offset_size-1 downto 0) := (others=>'0');
-- output signals
signal output_aer : std_logic_vector(log_b(output_neuron, 2)-1 downto 0);
signal output_spike_flag : std_logic;
......@@ -207,9 +202,9 @@ begin
for I in 0 to output_neuron-1 loop
w := data_read((I*weight_size)+weight_size-1 downto I*weight_size);
if weight_signed then
current_array(I) <= std_logic_vector(signed(current_array(I)) + signed((unsigned(w)&unsigned(weight_offset))));
current_array(I) <= std_logic_vector(signed(current_array(I)) + signed(w));
else
current_array(I) <= std_logic_vector(unsigned(current_array(I)) + unsigned((unsigned(w)&unsigned(weight_offset))));
current_array(I) <= std_logic_vector(unsigned(current_array(I)) + unsigned(w));
end if;
end loop;
end if;
......@@ -232,9 +227,9 @@ begin
for I in 0 to output_neuron-1 loop
w_rec := rec_data_read((I*weight_size)+weight_size-1 downto I*weight_size);
if weight_signed then
rec_current_array(I) <= std_logic_vector(signed(rec_current_array(I)) + signed((unsigned(w_rec)&unsigned(weight_offset))));
rec_current_array(I) <= std_logic_vector(signed(rec_current_array(I)) + signed(w_rec));
else
rec_current_array(I) <= std_logic_vector(unsigned(rec_current_array(I)) + unsigned((unsigned(w_rec)&unsigned(weight_offset))));
rec_current_array(I) <= std_logic_vector(unsigned(rec_current_array(I)) + unsigned(w_rec));
end if;
end loop;
end if;
......@@ -331,10 +326,10 @@ begin
when emulate => -- emulation state
if weight_signed then
v_mult := std_logic_vector(signed(v)*signed(beta));
v_next := v_mult(compute_fp+variable_size-1 downto compute_fp);
v_next := v_mult(fixed_point+variable_size-1 downto fixed_point);
else
v_mult := std_logic_vector(unsigned(v)*unsigned(beta));
v_next := v_mult(compute_fp+variable_size-1 downto compute_fp);
v_next := v_mult(fixed_point+variable_size-1 downto fixed_point);
end if;
transmission_state <= set_voltage;
......
......@@ -32,11 +32,9 @@ entity RShiftLif_Parallel is
v_threshold : std_logic_vector;
shift : integer;
reset : string := "zero";
compute_fp : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false;
weight_fp : integer := 1;
mem_init_file : string := "none";
mem_init_file_rec : string := ""
......@@ -106,11 +104,9 @@ architecture Behavioral of RShiftLif_Parallel is
v_threshold : std_logic_vector;
shift : integer;
reset : string := "zero";
compute_fp : integer := 8;
weight_size : integer := 2;
weight_signed : boolean := false;
weight_fp : integer := 1
weight_signed : boolean := false
);
Port (
i_clk : in std_logic;
......@@ -362,10 +358,8 @@ begin
v_threshold => v_threshold,
shift => shift,
reset => reset,
compute_fp => compute_fp,
weight_size => weight_size,
weight_signed => weight_signed,
weight_fp => weight_fp
weight_signed => weight_signed
) port map(
i_clk=>i_clk,
i_en=>neuron_en,
......
......@@ -35,11 +35,9 @@ entity RShiftLif_Sequential is
v_threshold : std_logic_vector;
shift : integer := 4;
reset : string := "zero";
compute_fp : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false; -- w_unsigned or w_signed
weight_fp : integer := 1;
weight_signed : boolean := false;
mem_init_file : string := "none";
mem_init_file_rec : string := ""
......@@ -90,10 +88,6 @@ architecture Behavioral of RShiftLif_Sequential is
type reception_state_t is (idle, request, wait_data, get_data, update_current);
type transmission_state_t is (idle, request, accept, get_voltage, emulate, set_voltage, emulate_finish);
-- weight offset definition
constant weight_offset_size : integer := compute_fp-weight_fp;
signal weight_offset : std_logic_vector(weight_offset_size-1 downto 0) := (others=>'0');
-- output signals
signal output_aer : std_logic_vector(log_b(output_neuron, 2)-1 downto 0);
signal output_spike_flag : std_logic;
......@@ -205,9 +199,9 @@ begin
for I in 0 to output_neuron-1 loop
w := data_read((I*weight_size)+weight_size-1 downto I*weight_size);
if weight_signed then
current_array(I) <= std_logic_vector(signed(current_array(I)) + signed((unsigned(w)&unsigned(weight_offset))));
current_array(I) <= std_logic_vector(signed(current_array(I)) + signed(w));
else
current_array(I) <= std_logic_vector(unsigned(current_array(I)) + unsigned((unsigned(w)&unsigned(weight_offset))));
current_array(I) <= std_logic_vector(unsigned(current_array(I)) + unsigned(w));
end if;
end loop;
end if;
......@@ -230,9 +224,9 @@ begin
for I in 0 to output_neuron-1 loop
w_rec := rec_data_read((I*weight_size)+weight_size-1 downto I*weight_size);
if weight_signed then
rec_current_array(I) <= std_logic_vector(signed(rec_current_array(I)) + signed((unsigned(w_rec)&unsigned(weight_offset))));
rec_current_array(I) <= std_logic_vector(signed(rec_current_array(I)) + signed(w_rec));
else
rec_current_array(I) <= std_logic_vector(unsigned(rec_current_array(I)) + unsigned((unsigned(w_rec)&unsigned(weight_offset))));
rec_current_array(I) <= std_logic_vector(unsigned(rec_current_array(I)) + unsigned(w_rec));
end if;
end loop;
end if;
......
......@@ -29,11 +29,9 @@ entity shift_lif is
v_threshold : std_logic_vector;
shift : integer;
reset : string := "zero";
compute_fp : integer := 8;
weight_size : integer := 2;
weight_signed : boolean := false;
weight_fp : integer := 1
weight_signed : boolean := false
);
Port (
i_clk : in std_logic;
......@@ -56,9 +54,6 @@ end shift_lif;
architecture Behavioral of shift_lif is
constant weight_offset_size : integer := compute_fp-weight_fp;
constant weight_offset : std_logic_vector(weight_offset_size-1 downto 0) := (others=>'0');
signal spike : std_logic := '0';
-- weight register signals
......@@ -84,11 +79,11 @@ begin
if weight_signed then
if spike_flag = '1' or spike_flag_rec = '1' then
if spike_flag = '1' and spike_flag_rec = '0' then
V <= std_logic_vector(signed(V) + signed(weight&weight_offset));
V <= std_logic_vector(signed(V) + signed(weight));
elsif spike_flag = '0' and spike_flag_rec = '1' then
V <= std_logic_vector(signed(V) + signed(weight_rec&weight_offset));
V <= std_logic_vector(signed(V) + signed(weight_rec));
else
V <= std_logic_vector(signed(V) + signed(weight&weight_offset) + signed(weight_rec&weight_offset));
V <= std_logic_vector(signed(V) + signed(weight) + signed(weight_rec));
end if;
elsif i_calc='1' then
if signed(V) >= signed(v_threshold) then
......@@ -106,11 +101,11 @@ begin
else
if spike_flag = '1' or spike_flag_rec = '1' then
if spike_flag = '1' and spike_flag_rec = '0' then
V <= std_logic_vector(unsigned(V) + unsigned(weight&weight_offset));
V <= std_logic_vector(unsigned(V) + unsigned(weight));
elsif spike_flag = '0' and spike_flag_rec = '1' then
V <= std_logic_vector(unsigned(V) + unsigned(weight_rec&weight_offset));
V <= std_logic_vector(unsigned(V) + unsigned(weight_rec));
else
V <= std_logic_vector(unsigned(V) + unsigned(weight&weight_offset) + unsigned(weight_rec&weight_offset));
V <= std_logic_vector(unsigned(V) + unsigned(weight) + unsigned(weight_rec));
end if;
elsif i_calc='1' then
if unsigned(V) >= unsigned(v_threshold) then
......
......@@ -32,11 +32,9 @@ entity ShiftLif_Parallel is
v_threshold : std_logic_vector;
shift : integer;
reset : string := "zero";
compute_fp : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false;
weight_fp : integer := 1;
mem_init_file : string := "none"
);
......@@ -105,11 +103,9 @@ architecture Behavioral of ShiftLif_Parallel is
v_threshold : std_logic_vector;
shift : integer;
reset : string := "zero";
compute_fp : integer := 8;
weight_size : integer := 2;
weight_signed : boolean := false;
weight_fp : integer := 1
weight_signed : boolean := false
);
Port (
i_clk : in std_logic;
......@@ -327,10 +323,8 @@ begin
v_threshold => v_threshold,
shift => shift,
reset => reset,
compute_fp => compute_fp,
weight_size => weight_size,
weight_signed => weight_signed,
weight_fp => weight_fp
weight_signed => weight_signed
) port map(
i_clk=>i_clk,
i_en=>neuron_en,
......
......@@ -35,12 +35,10 @@ entity ShiftLif_Sequential is
v_threshold : std_logic_vector;
shift : integer := 4;
reset : string := "zero";
compute_fp : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false; -- w_unsigned or w_signed
weight_fp : integer := 1;
weight_signed : boolean := false;
mem_init_file : string := "none"
);
......@@ -85,10 +83,6 @@ architecture Behavioral of ShiftLif_Sequential is
);
end component;
-- weight offset definition
constant weight_offset_size : integer := compute_fp-weight_fp;
constant weight_offset : std_logic_vector(weight_offset_size-1 downto 0) := (others=>'0');
-- type definition
type array_t is array(output_neuron-1 downto 0) of std_logic_vector(variable_size-1 downto 0);
type reception_state_t is (idle, request, wait_data, get_data, update_current);
......@@ -193,9 +187,9 @@ begin
for I in 0 to output_neuron-1 loop
w := data_read((I*weight_size)+weight_size-1 downto I*weight_size);
if weight_signed then
current_array(I) <= std_logic_vector(signed(current_array(I)) + signed((unsigned(w)&unsigned(weight_offset))));
current_array(I) <= std_logic_vector(signed(current_array(I)) + signed(w));
else
current_array(I) <= std_logic_vector(unsigned(current_array(I)) + unsigned((unsigned(w)&unsigned(weight_offset))));
current_array(I) <= std_logic_vector(unsigned(current_array(I)) + unsigned(w));
end if;
end loop;
end if;
......
......@@ -23,11 +23,10 @@ _BLIF_DEFINITION = """
v_threshold : std_logic_vector;
beta : std_logic_vector;
reset : string := "zero";
compute_fp : integer := 8;
fixed_point : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false;
weight_fp : integer := 1;
mem_init_file : string := "none"
);
......@@ -268,10 +267,9 @@ class BLif(ModNEFArchMod):
vhdl_file.write(f"\t\tv_threshold => x\"{self._to_hex(self.v_threshold, self.variable_size)}\",\n")
vhdl_file.write(f"\t\tbeta => x\"{self._to_hex(self.beta, self.variable_size)}\",\n")
vhdl_file.write(f"\t\treset => \"{self.reset}\",\n")
vhdl_file.write(f"\t\tcompute_fp => {self.quantizer.fixed_point},\n")
vhdl_file.write(f"\t\tfixed_point => {self.quantizer.fixed_point},\n")
vhdl_file.write(f"\t\tweight_size => {self.quantizer.bitwidth},\n")
vhdl_file.write(f"\t\tweight_signed => {self.quantizer.signed},\n")
vhdl_file.write(f"\t\tweight_fp => {self.quantizer.fixed_point},\n")
vhdl_file.write(f"\t\tmem_init_file => \"{self.mem_init_file}\"\n")
vhdl_file.write("\t) port map(\n")
vhdl_file.write(f"\t\ti_clk => {clock_name},\n")
......
......@@ -22,11 +22,10 @@ _RBLIF_DEFINITION = """
v_threshold : std_logic_vector;
beta : std_logic_vector;
reset : string := "zero";
compute_fp : integer := 8;
fixed_point : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false;
weight_fp : integer := 1;
mem_init_file : string := "none";
mem_init_file_rec : string := ""
......@@ -286,10 +285,9 @@ class RBLif(ModNEFArchMod):
vhdl_file.write(f"\t\tv_threshold => x\"{self._to_hex(self.v_threshold, self.variable_size)}\",\n")
vhdl_file.write(f"\t\tbeta => x\"{self._to_hex(self.beta, self.variable_size)}\",\n")
vhdl_file.write(f"\t\treset => \"{self.reset}\",\n")
vhdl_file.write(f"\t\tcompute_fp => {self.quantizer.fixed_point},\n")
vhdl_file.write(f"\t\tfixed_point => {self.quantizer.fixed_point},\n")
vhdl_file.write(f"\t\tweight_size => {self.quantizer.bitwidth},\n")
vhdl_file.write(f"\t\tweight_signed => {self.quantizer.signed},\n")
vhdl_file.write(f"\t\tweight_fp => {self.quantizer.fixed_point},\n")
vhdl_file.write(f"\t\tmem_init_file => \"{self.mem_init_file}\",\n")
vhdl_file.write(f"\t\tmem_init_file_rec => \"{self.mem_init_file_rec}\"\n")
vhdl_file.write("\t) port map(\n")
......
......@@ -23,11 +23,9 @@ _RSHIFTLIF_DEFINITION = """
v_threshold : std_logic_vector;
shift : integer;
reset : string := "zero";
compute_fp : integer := 8;
weight_size : integer := 1;
weight_signed : boolean := false;
weight_fp : integer := 1;
mem_init_file : string := "none";
mem_init_file_rec : string := ""
......@@ -286,10 +284,8 @@ class RShiftLif(ModNEFArchMod):
vhdl_file.write(f"\t\tv_threshold => x\"{self._to_hex(self.v_threshold, self.variable_size)}\",\n")
vhdl_file.write(f"\t\tshift => {self.shift},\n")
vhdl_file.write(f"\t\treset => \"{self.reset}\",\n")
vhdl_file.write(f"\t\tcompute_fp => {self.quantizer.bitwidth-1},\n")
vhdl_file.write(f"\t\tweight_size => {self.quantizer.bitwidth},\n")
vhdl_file.write(f"\t\tweight_signed => {self.quantizer.signed},\n")
vhdl_file.write(f"\t\tweight_fp => {self.quantizer.bitwidth-1},\n")
vhdl_file.write(f"\t\tmem_init_file => \"{self.mem_init_file}\",\n")
vhdl_file.write(f"\t\tmem_init_file_rec => \"{self.mem_init_file_rec}\"\n")
vhdl_file.write("\t) port map(\n")
......
......@@ -252,10 +252,8 @@ class ShiftLif(ModNEFArchMod):
vhdl_file.write(f"\t\tv_threshold => x\"{self._to_hex(self.v_threshold, self.variable_size)}\",\n")
vhdl_file.write(f"\t\tshift => {self.shift},\n")
vhdl_file.write(f"\t\treset => \"{self.reset}\",\n")
vhdl_file.write(f"\t\tcompute_fp => {self.quantizer.bitwidth-1},\n")
vhdl_file.write(f"\t\tweight_size => {self.quantizer.bitwidth},\n")
vhdl_file.write(f"\t\tweight_signed => {self.quantizer.signed},\n")
vhdl_file.write(f"\t\tweight_fp => {self.quantizer.bitwidth-1},\n")
vhdl_file.write(f"\t\tmem_init_file => \"{self.mem_init_file}\"\n")
vhdl_file.write("\t) port map(\n")
vhdl_file.write(f"\t\ti_clk => {clock_name},\n")
......
......@@ -315,6 +315,7 @@ class RShiftLIF(LIF, ModNEFNeuron):
else:
self.hardware_description["variable_size"]=16
module = builder.RShiftLif(
name=module_name,
input_neuron=self.fc.in_features,
......
......@@ -340,7 +340,6 @@ class ShiftLIF(LIF, ModNEFNeuron):
self.quantizer.init_from_weight(weight=self.fc.weight)
self.threshold.data = self.quantizer(self.threshold.data, True)
self.beta.data = self.quantizer(self.beta.data, True)
def quantize(self, force_init=False):
"""
......
......@@ -165,7 +165,15 @@ class FixedPointQuantizer(Quantizer):
scaled = torch.round(data*self.scale_factor).to(self.dtype)
#scaled = torch.clamp(scaled, -2**(self.bitwidth-1), 2**(self.bitwidth-1)-1)
if unscale:
return (scaled.to(torch.float32))/self.scale_factor
else:
return scaled
def _clamp(self, data):
b_min = (-2**(self.bitwidth-int(self.signed))*int(self.signed))/self.scale_factor
b_max = (2**(self.bitwidth-int(self.signed))-1)/self.scale_factor
return torch.clamp(data, min=b_min, max=b_max)
\ No newline at end of file
......@@ -135,3 +135,38 @@ class Quantizer():
"""
pass
def clamp(self, data):
"""
Call quantization function
Parameters
----------
data : int | float | list | numpy.array | Tensor
data to quantize
unscale = False : bool
If true, apply quantization and then, unquantize data to simulate quantization
Returns
-------
int | float | list | numpy.array | Tensor (depending on type of data)
"""
b_min = -1 #(-2**(self.bitwidth-int(self.signed))*int(self.signed))
b_max = 1 #2**(self.bitwidth-int(self.signed))-1
if isinstance(data, (int, float)):
return self._clamp(torch.tensor(data)).item()
elif isinstance(data, list):
return self._clamp(torch.tensor(data)).tolist()
elif isinstance(data, np.ndarray):
return self._clamp(torch.tensor(data)).numpy()
elif torch.is_tensor(data):
return self._clamp(data).detach()
else:
raise TypeError("Unsupported data type")
def _clamp(self, data):
raise NotImplementedError()
\ No newline at end of file
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