diff --git a/tp5_n/tp5_n.cache/wt/webtalk_pa.xml b/tp5_n/tp5_n.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000000000000000000000000000000000000..6673affa55f49514a883ae75f7a522d49ff67e77 --- /dev/null +++ b/tp5_n/tp5_n.cache/wt/webtalk_pa.xml @@ -0,0 +1,107 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<document> +<!--The data in this file is primarily intended for consumption by Xilinx tools. +The structure and the elements are likely to change over the next few releases. +This means code written to parse this file will need to be revisited each subsequent release.--> +<application name="pa" timeStamp="Tue Apr 22 17:35:19 2025"> +<section name="Project Information" visible="false"> +<property name="ProjectID" value="1b11cba828a44658b54f60d00c70dab6" type="ProjectID"/> +<property name="ProjectIteration" value="44" type="ProjectIteration"/> +</section> +<section name="PlanAhead Usage" visible="true"> +<item name="Project Data"> +<property name="SrcSetCount" value="1" type="SrcSetCount"/> +<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/> +<property name="DesignMode" value="RTL" type="DesignMode"/> +<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/> +<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> +</item> +<item name="Java Command Handlers"> +<property name="AddSources" value="9" type="JavaHandler"/> +<property name="AutoConnectTarget" value="3" type="JavaHandler"/> +<property name="CloseProject" value="1" type="JavaHandler"/> +<property name="CreateHardwareDashboards" value="2" type="JavaHandler"/> +<property name="EditDelete" value="2" type="JavaHandler"/> +<property name="ExitApp" value="1" type="JavaHandler"/> +<property name="LaunchProgramFpga" value="11" type="JavaHandler"/> +<property name="OpenHardwareManager" value="3" type="JavaHandler"/> +<property name="OpenRecentTarget" value="1" type="JavaHandler"/> +<property name="ProgramDevice" value="1" type="JavaHandler"/> +<property name="RunBitgen" value="11" type="JavaHandler"/> +<property name="RunImplementation" value="2" type="JavaHandler"/> +<property name="RunSchematic" value="1" type="JavaHandler"/> +<property name="RunSynthesis" value="7" type="JavaHandler"/> +<property name="SaveFileProxyHandler" value="10" type="JavaHandler"/> +<property name="SetTopNode" value="2" type="JavaHandler"/> +<property name="ShowView" value="16" type="JavaHandler"/> +<property name="SimulationRun" value="3" type="JavaHandler"/> +<property name="SimulationRunForTime" value="20" type="JavaHandler"/> +<property name="ToolsTemplates" value="2" type="JavaHandler"/> +<property name="ViewTaskImplementation" value="1" type="JavaHandler"/> +<property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/> +<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/> +<property name="ZoomIn" value="5" type="JavaHandler"/> +</item> +<item name="Gui Handlers"> +<property name="AbstractCombinedPanel_ADD_ELEMENT" value="3" type="GuiHandlerData"/> +<property name="AbstractSearchablePanel_SHOW_SEARCH" value="1" type="GuiHandlerData"/> +<property name="AddSrcWizard_SPECIFY_OR_CREATE_CONSTRAINT_FILES" value="1" type="GuiHandlerData"/> +<property name="BaseDialog_CANCEL" value="2" type="GuiHandlerData"/> +<property name="BaseDialog_CLOSE" value="2" type="GuiHandlerData"/> +<property name="BaseDialog_OK" value="68" type="GuiHandlerData"/> +<property name="BaseDialog_YES" value="10" type="GuiHandlerData"/> +<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/> +<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/> +<property name="CreateSrcFileDialog_FILE_NAME" value="7" type="GuiHandlerData"/> +<property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="26" type="GuiHandlerData"/> +<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="128" type="GuiHandlerData"/> +<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="41" type="GuiHandlerData"/> +<property name="HInputHandler_SELECT_ALL" value="1" type="GuiHandlerData"/> +<property name="HJFileChooserRecentListPreview_RECENT_DIRECTORIES" value="1" type="GuiHandlerData"/> +<property name="LanguageTemplatesDialog_TEMPLATES_TREE" value="4" type="GuiHandlerData"/> +<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/> +<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/> +<property name="MainMenuMgr_PROJECT" value="1" type="GuiHandlerData"/> +<property name="MainMenuMgr_TOOLS" value="4" type="GuiHandlerData"/> +<property name="PACommandNames_ADD_CONFIG_MEMORY" value="1" type="GuiHandlerData"/> +<property name="PACommandNames_ADD_SOURCES" value="9" type="GuiHandlerData"/> +<property name="PACommandNames_AUTO_CONNECT_TARGET" value="3" type="GuiHandlerData"/> +<property name="PACommandNames_AUTO_UPDATE_HIER" value="3" type="GuiHandlerData"/> +<property name="PACommandNames_CREATE_HARDWARE_DASHBOARDS" value="2" type="GuiHandlerData"/> +<property name="PACommandNames_GOTO_IMPLEMENTED_DESIGN" value="1" type="GuiHandlerData"/> +<property name="PACommandNames_LANGUAGE_TEMPLATES" value="2" type="GuiHandlerData"/> +<property name="PACommandNames_OPEN_HARDWARE_MANAGER" value="2" type="GuiHandlerData"/> +<property name="PACommandNames_PROGRAM_FPGA" value="1" type="GuiHandlerData"/> +<property name="PACommandNames_REPORTS_WINDOW" value="3" type="GuiHandlerData"/> +<property name="PACommandNames_SET_AS_TOP" value="2" type="GuiHandlerData"/> +<property name="PACommandNames_SIMULATION_LIVE_RUN" value="19" type="GuiHandlerData"/> +<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="3" type="GuiHandlerData"/> +<property name="PACommandNames_ZOOM_IN" value="2" type="GuiHandlerData"/> +<property name="PAViews_PROJECT_SUMMARY" value="6" type="GuiHandlerData"/> +<property name="ProgramDebugTab_OPEN_TARGET" value="3" type="GuiHandlerData"/> +<property name="ProgramDebugTab_PROGRAM_DEVICE" value="11" type="GuiHandlerData"/> +<property name="ProgramDebugTab_REFRESH_DEVICE" value="1" type="GuiHandlerData"/> +<property name="ProgramFpgaDialog_PROGRAM" value="11" type="GuiHandlerData"/> +<property name="RDICommands_CUSTOM_COMMANDS" value="2" type="GuiHandlerData"/> +<property name="RDICommands_DELETE" value="2" type="GuiHandlerData"/> +<property name="RDICommands_LINE_COMMENT" value="15" type="GuiHandlerData"/> +<property name="RDICommands_PASTE" value="1" type="GuiHandlerData"/> +<property name="RemoveSourcesDialog_ALSO_DELETE" value="1" type="GuiHandlerData"/> +<property name="SchematicView_PREVIOUS" value="3" type="GuiHandlerData"/> +<property name="SchematicView_REMOVE" value="2" type="GuiHandlerData"/> +<property name="SimulationForceSettingsDialog_FORCE_VALUE" value="8" type="GuiHandlerData"/> +<property name="SimulationLiveRunForComp_SPECIFY_TIME_AND_UNITS" value="2" type="GuiHandlerData"/> +<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="1" type="GuiHandlerData"/> +<property name="SrcChooserPanel_CREATE_FILE" value="7" type="GuiHandlerData"/> +<property name="SrcMenu_IP_HIERARCHY" value="3" type="GuiHandlerData"/> +<property name="TaskBanner_CLOSE" value="3" type="GuiHandlerData"/> +<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="27" type="GuiHandlerData"/> +</item> +<item name="Other"> +<property name="GuiMode" value="10" type="GuiMode"/> +<property name="BatchMode" value="0" type="BatchMode"/> +<property name="TclMode" value="6" type="TclMode"/> +</item> +</section> +</application> +</document> diff --git a/tp5_n/tp5_n.hw/hw_1/hw.xml b/tp5_n/tp5_n.hw/hw_1/hw.xml new file mode 100644 index 0000000000000000000000000000000000000000..6e1f7774a44fb3e28e88df05be7836e0e04f2326 --- /dev/null +++ b/tp5_n/tp5_n.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2021.1 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. --> + +<hwsession version="1" minor="2"> + <device name="xc7a35t_0" gui_info=""/> + <ObjectList object_type="hw_device" gui_info=""> + <Object name="xc7a35t_0" gui_info=""> + <Properties Property="FULL_PROBES.FILE" value=""/> + <Properties Property="PROBES.FILE" value=""/> + <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/digi_code.bit"/> + <Properties Property="SLR.COUNT" value="1"/> + </Object> + </ObjectList> + <probeset name="hw project" active="false"/> +</hwsession> diff --git a/tp5_n/tp5_n.hw/webtalk/usage_statistics_ext_labtool.xml b/tp5_n/tp5_n.hw/webtalk/usage_statistics_ext_labtool.xml new file mode 100644 index 0000000000000000000000000000000000000000..4427e4e9d9590fd9d372a701b2b44e0c6dfe771e --- /dev/null +++ b/tp5_n/tp5_n.hw/webtalk/usage_statistics_ext_labtool.xml @@ -0,0 +1,39 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<webTalkData fileName='usage_statistics_ext_labtool.xml' majorVersion='1' minorVersion='0' timeStamp='Tue Apr 22 17:35:21 2025'> +<section name="__ROOT__" level="0" order="1" description=""> + <section name="software_version_and_target_device" level="1" order="1" description=""> + <keyValuePair key="beta" value="FALSE" description="" /> + <keyValuePair key="build_version" value="3247384" description="" /> + <keyValuePair key="date_generated" value="Tue Apr 22 13:53:37 2025" description="" /> + <keyValuePair key="os_platform" value="LIN64" description="" /> + <keyValuePair key="product_version" value="Vivado v2021.1 (64-bit)" description="" /> + <keyValuePair key="project_id" value="19ee4622-bf11-4c31-9f35-1c5025d06df3" description="" /> + <keyValuePair key="project_iteration" value="1" description="" /> + <keyValuePair key="random_id" value="de56566a-b2bc-4a18-83fc-bac049cb8ae2" description="" /> + <keyValuePair key="registration_id" value="de56566a-b2bc-4a18-83fc-bac049cb8ae2" description="" /> + <keyValuePair key="route_design" value="FALSE" description="" /> + <keyValuePair key="target_device" value="not_applicable" description="" /> + <keyValuePair key="target_family" value="not_applicable" description="" /> + <keyValuePair key="target_package" value="not_applicable" description="" /> + <keyValuePair key="target_speed" value="not_applicable" description="" /> + <keyValuePair key="tool_flow" value="labtool" description="" /> + </section> + <section name="user_environment" level="1" order="2" description=""> + <keyValuePair key="cpu_name" value="Intel(R) Core(TM) i5-9500 CPU @ 3.00GHz" description="" /> + <keyValuePair key="cpu_speed" value="4099.904 MHz" description="" /> + <keyValuePair key="os_name" value="Ubuntu" description="" /> + <keyValuePair key="os_release" value="Ubuntu 22.04.5 LTS" description="" /> + <keyValuePair key="system_ram" value="16.000 GB" description="" /> + <keyValuePair key="total_processors" value="1" description="" /> + </section> + <section name="labtool" level="1" order="3" description=""> + <section name="usage" level="2" order="1" description=""> + <keyValuePair key="cable" value="Digilent/Basys3/15000000:" description="" /> + <keyValuePair key="chain" value="0362D093" description="" /> + <keyValuePair key="pgmcnt" value="05:00:00" description="" /> + </section> + </section> + <section name="vivado_usage" level="1" order="4" description=""> + </section> +</section> +</webTalkData> diff --git a/tp5_n/tp5_n.ip_user_files/README.txt b/tp5_n/tp5_n.ip_user_files/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..023052cab505345c50834e560e42db8c25daf798 --- /dev/null +++ b/tp5_n/tp5_n.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_1.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000000000000000000000000000000000000..287f6c3e44ecf071c6ff4d965cca067e337e8287 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,12 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Run Id="impl_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"> + <Parent Id="synth_1"/> + </Run> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_10.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000000000000000000000000000000000000..01ada7f44cd3dfa70f0c63e8e2c2d058f8a79ab7 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,9 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_11.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000000000000000000000000000000000000..01ada7f44cd3dfa70f0c63e8e2c2d058f8a79ab7 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,9 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_12.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000000000000000000000000000000000000..01ada7f44cd3dfa70f0c63e8e2c2d058f8a79ab7 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,9 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_13.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000000000000000000000000000000000000..01ada7f44cd3dfa70f0c63e8e2c2d058f8a79ab7 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,9 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_14.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000000000000000000000000000000000000..01ada7f44cd3dfa70f0c63e8e2c2d058f8a79ab7 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,9 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_2.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000000000000000000000000000000000000..287f6c3e44ecf071c6ff4d965cca067e337e8287 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,12 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Run Id="impl_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"> + <Parent Id="synth_1"/> + </Run> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_3.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000000000000000000000000000000000000..287f6c3e44ecf071c6ff4d965cca067e337e8287 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,12 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Run Id="impl_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"> + <Parent Id="synth_1"/> + </Run> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_4.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000000000000000000000000000000000000..287f6c3e44ecf071c6ff4d965cca067e337e8287 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,12 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Run Id="impl_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"> + <Parent Id="synth_1"/> + </Run> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_5.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000000000000000000000000000000000000..287f6c3e44ecf071c6ff4d965cca067e337e8287 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,12 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Run Id="impl_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"> + <Parent Id="synth_1"/> + </Run> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_6.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000000000000000000000000000000000000..287f6c3e44ecf071c6ff4d965cca067e337e8287 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,12 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Run Id="impl_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"> + <Parent Id="synth_1"/> + </Run> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_7.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000000000000000000000000000000000000..287f6c3e44ecf071c6ff4d965cca067e337e8287 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,12 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Run Id="impl_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"> + <Parent Id="synth_1"/> + </Run> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_8.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000000000000000000000000000000000000..287f6c3e44ecf071c6ff4d965cca067e337e8287 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,12 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Run Id="impl_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"> + <Parent Id="synth_1"/> + </Run> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_9.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000000000000000000000000000000000000..287f6c3e44ecf071c6ff4d965cca067e337e8287 --- /dev/null +++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,12 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Run Id="impl_1" LaunchDir="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"> + <Parent Id="synth_1"/> + </Run> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + </Parameters> +</Runs> + diff --git a/tp5_n/tp5_n.runs/synth_1/.Xil/anti_rebond_propImpl.xdc b/tp5_n/tp5_n.runs/synth_1/.Xil/anti_rebond_propImpl.xdc new file mode 100644 index 0000000000000000000000000000000000000000..95f43f158aab560fcd4ca52d0acd0d5dff77cf46 --- /dev/null +++ b/tp5_n/tp5_n.runs/synth_1/.Xil/anti_rebond_propImpl.xdc @@ -0,0 +1,63 @@ +set_property SRC_FILE_INFO {cfile:/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc rfile:../../../tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W5 [get_ports clk] +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V17 [get_ports {sw[0]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V16 [get_ports {sw[1]}] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W16 [get_ports {sw[2]}] +set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W17 [get_ports {sw[3]}] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W15 [get_ports {sw[4]}] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V15 [get_ports {sw[5]}] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W14 [get_ports {sw[6]}] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W13 [get_ports {sw[7]}] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U16 [get_ports {led[0]}] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E19 [get_ports {led[1]}] +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U18 [get_ports btnC] +set_property src_info {type:XDC file:1 line:112 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports btnC] +set_property src_info {type:XDC file:1 line:113 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T18 [get_ports btnU] +set_property src_info {type:XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports btnU] +set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W19 [get_ports btnL] +set_property src_info {type:XDC file:1 line:116 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports btnL] +set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T17 [get_ports btnR] +set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports btnR] +set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U17 [get_ports btnD] +set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design] +set_property IOSTANDARD LVCMOS33 [get_ports btnD] diff --git a/tp5_n/tp5_n.runs/synth_1/anti_rebond.dcp b/tp5_n/tp5_n.runs/synth_1/anti_rebond.dcp new file mode 100644 index 0000000000000000000000000000000000000000..7f59ccdf46eaaecf0f9a212652b1729ede3746c5 Binary files /dev/null and b/tp5_n/tp5_n.runs/synth_1/anti_rebond.dcp differ diff --git a/tp5_n/tp5_n.runs/synth_1/anti_rebond.tcl b/tp5_n/tp5_n.runs/synth_1/anti_rebond.tcl new file mode 100644 index 0000000000000000000000000000000000000000..19fed3a35f47480a07bcd97a86d1ee5383a9e58b --- /dev/null +++ b/tp5_n/tp5_n.runs/synth_1/anti_rebond.tcl @@ -0,0 +1,132 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/anti_rebond.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +OPTRACE "synth_1" START { ROLLUP_AUTO } +set_param chipscope.maxJobs 1 +set_param checkpoint.writeSynthRtdsInDcp 1 +set_param xicom.use_bs_reader 1 +set_param synth.incrementalSynthesisCache ./.Xil/Vivado-421777-b04p9/incrSyn +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7a35tcpg236-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.cache/wt [current_project] +set_property parent.project_path /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language VHDL [current_project] +set_property ip_output_repo /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_vhdl -library xil_defaultlib { + /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd + /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd + /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/fpde.vhd + /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/fpd.vhd +} +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc +set_property used_in_implementation false [get_files /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top anti_rebond -part xc7a35tcpg236-1 +OPTRACE "synth_design" END { } +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef anti_rebond.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +create_report "synth_1_synth_report_utilization_0" "report_utilization -file anti_rebond_utilization_synth.rpt -pb anti_rebond_utilization_synth.pb" +OPTRACE "synth reports" END { } +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "synth_1" END { } diff --git a/tp5_n/tp5_n.runs/synth_1/anti_rebond.vds b/tp5_n/tp5_n.runs/synth_1/anti_rebond.vds new file mode 100644 index 0000000000000000000000000000000000000000..93452fdb418ba759d37b572e7c03edcfa1f2d540 --- /dev/null +++ b/tp5_n/tp5_n.runs/synth_1/anti_rebond.vds @@ -0,0 +1,296 @@ +#----------------------------------------------------------- +# Vivado v2021.1 (64-bit) +# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021 +# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 +# Start of session at: Tue Apr 22 16:16:17 2025 +# Process ID: 497770 +# Current directory: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1 +# Command line: vivado -log anti_rebond.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source anti_rebond.tcl +# Log file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/anti_rebond.vds +# Journal file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/vivado.jou +#----------------------------------------------------------- +source anti_rebond.tcl -notrace +Command: synth_design -top anti_rebond -part xc7a35tcpg236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 497841 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2448.441 ; gain = 0.000 ; free physical = 578 ; free virtual = 7792 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'anti_rebond' [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:43] +INFO: [Synth 8-256] done synthesizing module 'anti_rebond' (1#1) [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:43] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2448.441 ; gain = 0.000 ; free physical = 220 ; free virtual = 6899 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2448.441 ; gain = 0.000 ; free physical = 203 ; free virtual = 6883 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2448.441 ; gain = 0.000 ; free physical = 203 ; free virtual = 6883 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2448.441 ; gain = 0.000 ; free physical = 198 ; free virtual = 6877 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc] +WARNING: [Vivado 12-584] No ports matched 'sw[0]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:12] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:12] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[0]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:13] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[1]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:14] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[1]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:15] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:15] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[2]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:16] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:16] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[2]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:17] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:17] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[3]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:18] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:18] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[3]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:19] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:19] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[4]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:20] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[4]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:21] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[5]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:22] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[5]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:23] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[6]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:24] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[6]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:25] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[7]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:26] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:26] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[7]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:27] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[0]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:47] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[0]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:48] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[1]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:49] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[1]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:50] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btnC'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:111] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:111] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btnC'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:112] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btnU'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:113] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btnU'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:114] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btnL'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:115] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btnL'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:116] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:116] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btnR'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:117] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btnR'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:118] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btnD'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:119] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btnD'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:120] +Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/anti_rebond_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/anti_rebond_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2496.309 ; gain = 0.000 ; free physical = 921 ; free virtual = 7610 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2496.309 ; gain = 0.000 ; free physical = 919 ; free virtual = 7609 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 984 ; free virtual = 7674 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 987 ; free virtual = 7676 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 987 ; free virtual = 7676 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 975 ; free virtual = 7666 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 6 Bit Registers := 1 + 1 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 963 ; free virtual = 7657 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 845 ; free virtual = 7537 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 845 ; free virtual = 7537 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 836 ; free virtual = 7528 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFG | 1| +|2 |LUT3 | 4| +|3 |FDRE | 7| +|4 |IBUF | 3| +|5 |OBUF | 1| ++------+-----+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2496.309 ; gain = 0.000 ; free physical = 885 ; free virtual = 7580 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 883 ; free virtual = 7578 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2496.309 ; gain = 0.000 ; free physical = 879 ; free virtual = 7574 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2496.309 ; gain = 0.000 ; free physical = 913 ; free virtual = 7608 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete, checksum: dc892547 +INFO: [Common 17-83] Releasing license: Synthesis +15 Infos, 30 Warnings, 30 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2496.309 ; gain = 48.023 ; free physical = 1065 ; free virtual = 7760 +INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING +INFO: [Common 17-1381] The checkpoint '/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/anti_rebond.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file anti_rebond_utilization_synth.rpt -pb anti_rebond_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Tue Apr 22 16:16:41 2025... diff --git a/tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.pb b/tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..dd8c36659fc8375eca6c825386eb31c600af0549 Binary files /dev/null and b/tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.pb differ diff --git a/tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.rpt b/tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.rpt new file mode 100644 index 0000000000000000000000000000000000000000..c007b807dcb5149e8d83d9c16fb428577bf208dd --- /dev/null +++ b/tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.rpt @@ -0,0 +1,175 @@ +Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021 +| Date : Tue Apr 22 16:16:41 2025 +| Host : b04p9 running 64-bit Ubuntu 22.04.5 LTS +| Command : report_utilization -file anti_rebond_utilization_synth.rpt -pb anti_rebond_utilization_synth.pb +| Design : anti_rebond +| Device : 7a35tcpg236-1 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs* | 3 | 0 | 0 | 20800 | 0.01 | +| LUT as Logic | 3 | 0 | 0 | 20800 | 0.01 | +| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 7 | 0 | 0 | 41600 | 0.02 | +| Register as Flip Flop | 7 | 0 | 0 | 41600 | 0.02 | +| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 7 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 4 | 0 | 0 | 106 | 3.77 | +| Bonded IPADs | 0 | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 0 | 20 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 7 | Flop & Latch | +| LUT3 | 4 | LUT | +| IBUF | 3 | IO | +| OBUF | 1 | IO | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/tp5_n/tp5_n.runs/synth_1/gen_run.xml b/tp5_n/tp5_n.runs/synth_1/gen_run.xml new file mode 100644 index 0000000000000000000000000000000000000000..573f3605b21da31288aa28bd999b6830badbf67a --- /dev/null +++ b/tp5_n/tp5_n.runs/synth_1/gen_run.xml @@ -0,0 +1,69 @@ +<?xml version="1.0" encoding="UTF-8"?> +<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1745331375"> + <File Type="VDS-TIMING-PB" Name="anti_rebond_timing_summary_synth.pb"/> + <File Type="VDS-TIMINGSUMMARY" Name="anti_rebond_timing_summary_synth.rpt"/> + <File Type="RDS-DCP" Name="anti_rebond.dcp"/> + <File Type="RDS-UTIL-PB" Name="anti_rebond_utilization_synth.pb"/> + <File Type="RDS-UTIL" Name="anti_rebond_utilization_synth.rpt"/> + <File Type="RDS-PROPCONSTRS" Name="anti_rebond_drc_synth.rpt"/> + <File Type="RDS-RDS" Name="anti_rebond.vds"/> + <File Type="REPORTS-TCL" Name="anti_rebond_reports.tcl"/> + <File Type="PA-TCL" Name="anti_rebond.tcl"/> + <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/new/digi_code.vhd"> + <FileInfo> + <Attr Name="ImportPath" Val="$PPRDIR/../Documents/HD/hardware_design/tp5/tp5.srcs/sources_1/new/digi_code.vhd"/> + <Attr Name="ImportTime" Val="1745321700"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/new/anti_rebond.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/new/fpde.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <File Path="$PSRCDIR/sources_1/new/fpd.vhd"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="anti_rebond"/> + </Config> + </FileSet> + <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> + <Filter Type="Constrs"/> + <File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys3_Master.xdc"> + <FileInfo> + <Attr Name="ImportPath" Val="$PPRDIR/../Documents/HD/hardware_design/tp_3/tp_3.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc"/> + <Attr Name="ImportTime" Val="1743511343"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + </FileInfo> + </File> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1"> + <Filter Type="Utils"/> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/> + <Step Id="synth_design"/> + </Strategy> +</GenRun> diff --git a/tp5_n/tp5_n.runs/synth_1/htr.txt b/tp5_n/tp5_n.runs/synth_1/htr.txt new file mode 100644 index 0000000000000000000000000000000000000000..b75ab37cc1d6b46874818fc4eab2b4fede846af4 --- /dev/null +++ b/tp5_n/tp5_n.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. +# + +vivado -log anti_rebond.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source anti_rebond.tcl diff --git a/tp5_n/tp5_n.runs/synth_1/vivado.jou b/tp5_n/tp5_n.runs/synth_1/vivado.jou new file mode 100644 index 0000000000000000000000000000000000000000..f123e8a30e50bd0cc702e15ab3defebee543bf59 --- /dev/null +++ b/tp5_n/tp5_n.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2021.1 (64-bit) +# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021 +# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 +# Start of session at: Tue Apr 22 16:16:17 2025 +# Process ID: 497770 +# Current directory: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1 +# Command line: vivado -log anti_rebond.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source anti_rebond.tcl +# Log file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/anti_rebond.vds +# Journal file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/vivado.jou +#----------------------------------------------------------- +source anti_rebond.tcl -notrace diff --git a/tp5_n/tp5_n.runs/synth_1/vivado.pb b/tp5_n/tp5_n.runs/synth_1/vivado.pb new file mode 100644 index 0000000000000000000000000000000000000000..514d904a788994349ef096c3c94834b12d88c129 Binary files /dev/null and b/tp5_n/tp5_n.runs/synth_1/vivado.pb differ diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/anti_rebond.tcl b/tp5_n/tp5_n.sim/sim_1/behav/xsim/anti_rebond.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/anti_rebond.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/anti_rebond_vhdl.prj b/tp5_n/tp5_n.sim/sim_1/behav/xsim/anti_rebond_vhdl.prj new file mode 100644 index 0000000000000000000000000000000000000000..43a80cca854c85c7eaa9ca3b29ecd7a899d09679 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/anti_rebond_vhdl.prj @@ -0,0 +1,9 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../tp5_n.srcs/sources_1/new/digi_code.vhd" \ +"../../../../tp5_n.srcs/sources_1/new/anti_rebond.vhd" \ +"../../../../tp5_n.srcs/sources_1/new/fpde.vhd" \ +"../../../../tp5_n.srcs/sources_1/new/fpd.vhd" \ + +# Do not sort compile order +nosort diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/chenillard.tcl b/tp5_n/tp5_n.sim/sim_1/behav/xsim/chenillard.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/chenillard.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/digi_code.tcl b/tp5_n/tp5_n.sim/sim_1/behav/xsim/digi_code.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/digi_code.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.jou b/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000000000000000000000000000000000000..db7acb7b56b55599f94d87bae6cb883064d24bf3 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2021.1 (64-bit) +# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021 +# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 +# Start of session at: Tue Apr 22 16:29:00 2025 +# Process ID: 503836 +# Current directory: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk_501609.backup.jou b/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk_501609.backup.jou new file mode 100644 index 0000000000000000000000000000000000000000..4d64edc05363e7109187eb759e944b7df0dc8020 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk_501609.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2021.1 (64-bit) +# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021 +# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 +# Start of session at: Tue Apr 22 16:24:51 2025 +# Process ID: 501609 +# Current directory: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk_501933.backup.jou b/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk_501933.backup.jou new file mode 100644 index 0000000000000000000000000000000000000000..29a965f52231d82197b4c1c6c37705e79cc60cf1 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk_501933.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2021.1 (64-bit) +# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021 +# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 +# Start of session at: Tue Apr 22 16:25:21 2025 +# Process ID: 501933 +# Current directory: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk_502528.backup.jou b/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk_502528.backup.jou new file mode 100644 index 0000000000000000000000000000000000000000..528c3112f3c2c61104666348ef026ab79653de41 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk_502528.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2021.1 (64-bit) +# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021 +# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021 +# Start of session at: Tue Apr 22 16:26:05 2025 +# Process ID: 502528 +# Current directory: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim +# Command line: wbtcv -mode batch -source /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.log +# Journal file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/webtalk.jou +#----------------------------------------------------------- +source /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xelab.pb b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000000000000000000000000000000000000..abf2a300e7c37c6b268968cc8bbd21a5f4bfb302 Binary files /dev/null and b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/Compile_Options.txt b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/Compile_Options.txt new file mode 100644 index 0000000000000000000000000000000000000000..be1ef8782193b36edddb5ad67f8c0ae91c29034e --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "5e5d1ac8df47476c870b4cf306020630" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "anti_rebond_behav" "xil_defaultlib.anti_rebond" -log "elaborate.log" diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/TempBreakPointFile.txt b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/TempBreakPointFile.txt new file mode 100644 index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/obj/xsim_1.c b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/obj/xsim_1.c new file mode 100644 index 0000000000000000000000000000000000000000..eca938120fc222916f67277b61107546534045b1 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/obj/xsim_1.c @@ -0,0 +1,110 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include <string.h> +#include <math.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include <string.h> +#include <math.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_12(char*, char *); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_2(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[5] = {(funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_2}; +const int NumRelocateId= 5; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/anti_rebond_behav/xsim.reloc", (void **)funcTab, 5); + iki_vhdl_file_variable_register(dp + 2984); + iki_vhdl_file_variable_register(dp + 3040); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/anti_rebond_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/anti_rebond_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/anti_rebond_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/anti_rebond_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/anti_rebond_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/usage_statistics_ext_xsim.xml b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000000000000000000000000000000000000..6d9740a8d95b461e5258ae7537c6c1be6c24f899 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Tue Apr 22 16:29:01 2025'> +<section name="__ROOT__" level="0" order="1" description=""> + <section name="software_version_and_target_device" level="1" order="1" description=""> + <keyValuePair key="beta" value="FALSE" description="" /> + <keyValuePair key="build_version" value="3247384" description="" /> + <keyValuePair key="date_generated" value="Tue Apr 22 16:28:59 2025" description="" /> + <keyValuePair key="os_platform" value="LIN64" description="" /> + <keyValuePair key="product_version" value="XSIM v2021.1 (64-bit)" description="" /> + <keyValuePair key="project_id" value="5e5d1ac8df47476c870b4cf306020630" description="" /> + <keyValuePair key="project_iteration" value="2" description="" /> + <keyValuePair key="random_id" value="de56566a-b2bc-4a18-83fc-bac049cb8ae2" description="" /> + <keyValuePair key="registration_id" value="de56566a-b2bc-4a18-83fc-bac049cb8ae2" description="" /> + <keyValuePair key="route_design" value="FALSE" description="" /> + <keyValuePair key="target_device" value="not_applicable" description="" /> + <keyValuePair key="target_family" value="not_applicable" description="" /> + <keyValuePair key="target_package" value="not_applicable" description="" /> + <keyValuePair key="target_speed" value="not_applicable" description="" /> + <keyValuePair key="tool_flow" value="xsim_vivado" description="" /> + </section> + <section name="user_environment" level="1" order="2" description=""> + <keyValuePair key="cpu_name" value="Intel(R) Core(TM) i5-9500 CPU @ 3.00GHz" description="" /> + <keyValuePair key="cpu_speed" value="3000.000 MHz" description="" /> + <keyValuePair key="os_name" value="Ubuntu" description="" /> + <keyValuePair key="os_release" value="Ubuntu 22.04.5 LTS" description="" /> + <keyValuePair key="system_ram" value="16.000 GB" description="" /> + <keyValuePair key="total_processors" value="1" description="" /> + </section> + <section name="vivado_usage" level="1" order="3" description=""> + </section> + <section name="xsim" level="1" order="4" description=""> + <section name="command_line_options" level="2" order="1" description=""> + <keyValuePair key="command" value="xsim" description="" /> + </section> + <section name="usage" level="2" order="2" description=""> + <keyValuePair key="iteration" value="2" description="" /> + <keyValuePair key="runtime" value="2902410410 ns" description="" /> + <keyValuePair key="simulation_memory" value="116400_KB" description="" /> + <keyValuePair key="simulation_time" value="10.48_sec" description="" /> + <keyValuePair key="trace_waveform" value="true" description="" /> + </section> + </section> +</section> +</webTalkData> diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/xsim_webtalk.tcl b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000000000000000000000000000000000000..c38b2fe3e42198481c412da658d176b1bae3c063 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Tue Apr 22 16:39:56 2025" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2021.1 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "3247384" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "de56566a-b2bc-4a18-83fc-bac049cb8ae2" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "5e5d1ac8df47476c870b4cf306020630" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" +webtalk_add_data -client project -key os_release -value "Ubuntu 22.04.5 LTS" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-9500 CPU @ 3.00GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3000.000 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "230 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "2" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "8.13_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "117384_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3790241870 -regid "" -xml /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>" +webtalk_terminate diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/xsim.mem b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/xsim.mem new file mode 100644 index 0000000000000000000000000000000000000000..e031b70fe39db3cefdc63a5b8edbd025601c1e28 Binary files /dev/null and b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/xsim.mem differ diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/Compile_Options.txt b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/Compile_Options.txt new file mode 100644 index 0000000000000000000000000000000000000000..00a17babacaf795b6d02523b06e817757f5d87fa --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "5e5d1ac8df47476c870b4cf306020630" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "digi_code_behav" "xil_defaultlib.digi_code" -log "elaborate.log" diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/TempBreakPointFile.txt b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/TempBreakPointFile.txt new file mode 100644 index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/obj/xsim_1.c b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/obj/xsim_1.c new file mode 100644 index 0000000000000000000000000000000000000000..398dad9b94d0fa7e584aac2d85dc51f4d5b0f44e --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/obj/xsim_1.c @@ -0,0 +1,111 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include <string.h> +#include <math.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include <string.h> +#include <math.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_8(char*, char *); +IKI_DLLESPEC extern void execute_9(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_6(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[6] = {(funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_6}; +const int NumRelocateId= 6; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/digi_code_behav/xsim.reloc", (void **)funcTab, 6); + iki_vhdl_file_variable_register(dp + 3952); + iki_vhdl_file_variable_register(dp + 4008); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/digi_code_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/digi_code_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/digi_code_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/digi_code_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/digi_code_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/webtalk/usage_statistics_ext_xsim.xml b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000000000000000000000000000000000000..75b1a7ca213da7458046102d27309ba289f5a580 --- /dev/null +++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Tue Apr 22 16:25:21 2025'> +<section name="__ROOT__" level="0" order="1" description=""> + <section name="software_version_and_target_device" level="1" order="1" description=""> + <keyValuePair key="beta" value="FALSE" description="" /> + <keyValuePair key="build_version" value="3247384" description="" /> + <keyValuePair key="date_generated" value="Tue Apr 22 16:25:20 2025" description="" /> + <keyValuePair key="os_platform" value="LIN64" description="" /> + <keyValuePair key="product_version" value="XSIM v2021.1 (64-bit)" description="" /> + <keyValuePair key="project_id" value="5e5d1ac8df47476c870b4cf306020630" description="" /> + <keyValuePair key="project_iteration" value="2" description="" /> + <keyValuePair key="random_id" value="de56566a-b2bc-4a18-83fc-bac049cb8ae2" description="" /> + <keyValuePair key="registration_id" value="de56566a-b2bc-4a18-83fc-bac049cb8ae2" description="" /> + <keyValuePair key="route_design" value="FALSE" description="" /> + <keyValuePair key="target_device" value="not_applicable" description="" /> + <keyValuePair key="target_family" value="not_applicable" description="" /> + <keyValuePair key="target_package" value="not_applicable" description="" /> + <keyValuePair key="target_speed" value="not_applicable" description="" /> + <keyValuePair key="tool_flow" value="xsim_vivado" description="" /> + </section> + <section name="user_environment" level="1" order="2" description=""> + <keyValuePair key="cpu_name" value="Intel(R) Core(TM) i5-9500 CPU @ 3.00GHz" description="" /> + <keyValuePair key="cpu_speed" value="3000.000 MHz" description="" /> + <keyValuePair key="os_name" value="Ubuntu" description="" /> + <keyValuePair key="os_release" value="Ubuntu 22.04.5 LTS" description="" /> + <keyValuePair key="system_ram" value="16.000 GB" description="" /> + <keyValuePair key="total_processors" value="1" description="" /> + </section> + <section name="vivado_usage" level="1" order="3" description=""> + </section> + <section name="xsim" level="1" order="4" description=""> + <section name="command_line_options" level="2" order="1" description=""> + <keyValuePair key="command" value="xsim" description="" /> + </section> + <section name="usage" level="2" order="2" description=""> + <keyValuePair key="iteration" value="0" description="" /> + <keyValuePair key="runtime" value="1 us" description="" /> + <keyValuePair key="simulation_memory" value="116412_KB" description="" /> + <keyValuePair key="simulation_time" value="0.05_sec" description="" /> + <keyValuePair key="trace_waveform" value="true" description="" /> + </section> + </section> +</section> +</webTalkData> diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/xsim.mem b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/xsim.mem new file mode 100644 index 0000000000000000000000000000000000000000..eb2e24f85c0ab0ef378997da68f50070fff53733 Binary files /dev/null and b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/digi_code_behav/xsim.mem differ diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xvhdl.pb b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xvhdl.pb new file mode 100644 index 0000000000000000000000000000000000000000..e4b98e59eb85bc5137030bb28f61eaaa600ac3bf Binary files /dev/null and b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xvhdl.pb differ diff --git a/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc b/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc new file mode 100644 index 0000000000000000000000000000000000000000..0978ac9d0d97644dedea7bda1812089026a04299 --- /dev/null +++ b/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc @@ -0,0 +1,295 @@ +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property PACKAGE_PIN W5 [get_ports clk] + set_property IOSTANDARD LVCMOS33 [get_ports clk] + create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] + +## Switches +set_property PACKAGE_PIN V17 [get_ports {sw[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +set_property PACKAGE_PIN V16 [get_ports {sw[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +set_property PACKAGE_PIN W16 [get_ports {sw[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +set_property PACKAGE_PIN W17 [get_ports {sw[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +set_property PACKAGE_PIN W15 [get_ports {sw[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +set_property PACKAGE_PIN V15 [get_ports {sw[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +set_property PACKAGE_PIN W14 [get_ports {sw[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] +set_property PACKAGE_PIN W13 [get_ports {sw[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +#set_property PACKAGE_PIN V2 [get_ports {sw[8]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +#set_property PACKAGE_PIN T3 [get_ports {sw[9]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +#set_property PACKAGE_PIN T2 [get_ports {sw[10]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +#set_property PACKAGE_PIN R3 [get_ports {sw[11]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +#set_property PACKAGE_PIN W2 [get_ports {sw[12]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +#set_property PACKAGE_PIN U1 [get_ports {sw[13]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +#set_property PACKAGE_PIN T1 [get_ports {sw[14]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +#set_property PACKAGE_PIN R2 [get_ports {sw[15]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + + +## LEDs +set_property PACKAGE_PIN U16 [get_ports {led[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +set_property PACKAGE_PIN E19 [get_ports {led[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +#set_property PACKAGE_PIN U19 [get_ports {led[2]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] +#set_property PACKAGE_PIN V19 [get_ports {led[3]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] +#set_property PACKAGE_PIN W18 [get_ports {led[4]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +#set_property PACKAGE_PIN U15 [get_ports {led[5]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +#set_property PACKAGE_PIN U14 [get_ports {led[6]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +#set_property PACKAGE_PIN V14 [get_ports {led[7]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +#set_property PACKAGE_PIN V13 [get_ports {led[8]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +#set_property PACKAGE_PIN V3 [get_ports {led[9]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +#set_property PACKAGE_PIN W3 [get_ports {led[10]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +#set_property PACKAGE_PIN U3 [get_ports {led[11]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +#set_property PACKAGE_PIN P3 [get_ports {led[12]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +#set_property PACKAGE_PIN N3 [get_ports {led[13]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +#set_property PACKAGE_PIN P1 [get_ports {led[14]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] +#set_property PACKAGE_PIN L1 [get_ports {led[15]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] + + +##7 segment display +#set_property PACKAGE_PIN W7 [get_ports {seg[0]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +#set_property PACKAGE_PIN W6 [get_ports {seg[1]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +#set_property PACKAGE_PIN U8 [get_ports {seg[2]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +#set_property PACKAGE_PIN V8 [get_ports {seg[3]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +#set_property PACKAGE_PIN U5 [get_ports {seg[4]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +#set_property PACKAGE_PIN V5 [get_ports {seg[5]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +#set_property PACKAGE_PIN U7 [get_ports {seg[6]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + +#set_property PACKAGE_PIN V7 [get_ports dp] +# set_property IOSTANDARD LVCMOS33 [get_ports dp] + +#set_property PACKAGE_PIN U2 [get_ports {an[0]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +#set_property PACKAGE_PIN U4 [get_ports {an[1]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +#set_property PACKAGE_PIN V4 [get_ports {an[2]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +#set_property PACKAGE_PIN W4 [get_ports {an[3]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] + + +##Buttons +set_property PACKAGE_PIN U18 [get_ports btnC] + set_property IOSTANDARD LVCMOS33 [get_ports btnC] +set_property PACKAGE_PIN T18 [get_ports btnU] + set_property IOSTANDARD LVCMOS33 [get_ports btnU] +set_property PACKAGE_PIN W19 [get_ports btnL] + set_property IOSTANDARD LVCMOS33 [get_ports btnL] +set_property PACKAGE_PIN T17 [get_ports btnR] + set_property IOSTANDARD LVCMOS33 [get_ports btnR] +set_property PACKAGE_PIN U17 [get_ports btnD] + set_property IOSTANDARD LVCMOS33 [get_ports btnD] + + + +##Pmod Header JA +##Sch name = JA1 +#set_property PACKAGE_PIN J1 [get_ports {JA[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] +##Sch name = JA2 +#set_property PACKAGE_PIN L2 [get_ports {JA[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] +##Sch name = JA3 +#set_property PACKAGE_PIN J2 [get_ports {JA[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] +##Sch name = JA4 +#set_property PACKAGE_PIN G2 [get_ports {JA[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] +##Sch name = JA7 +#set_property PACKAGE_PIN H1 [get_ports {JA[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] +##Sch name = JA8 +#set_property PACKAGE_PIN K2 [get_ports {JA[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] +##Sch name = JA9 +#set_property PACKAGE_PIN H2 [get_ports {JA[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] +##Sch name = JA10 +#set_property PACKAGE_PIN G3 [get_ports {JA[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + +##Pmod Header JB +##Sch name = JB1 +#set_property PACKAGE_PIN A14 [get_ports {JB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] +##Sch name = JB2 +#set_property PACKAGE_PIN A16 [get_ports {JB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] +##Sch name = JB3 +#set_property PACKAGE_PIN B15 [get_ports {JB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] +##Sch name = JB4 +#set_property PACKAGE_PIN B16 [get_ports {JB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] +##Sch name = JB7 +#set_property PACKAGE_PIN A15 [get_ports {JB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] +##Sch name = JB8 +#set_property PACKAGE_PIN A17 [get_ports {JB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] +##Sch name = JB9 +#set_property PACKAGE_PIN C15 [get_ports {JB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] +##Sch name = JB10 +#set_property PACKAGE_PIN C16 [get_ports {JB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + +##Pmod Header JC +##Sch name = JC1 +#set_property PACKAGE_PIN K17 [get_ports {JC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] +##Sch name = JC2 +#set_property PACKAGE_PIN M18 [get_ports {JC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] +##Sch name = JC3 +#set_property PACKAGE_PIN N17 [get_ports {JC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] +##Sch name = JC4 +#set_property PACKAGE_PIN P18 [get_ports {JC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] +##Sch name = JC7 +#set_property PACKAGE_PIN L17 [get_ports {JC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] +##Sch name = JC8 +#set_property PACKAGE_PIN M19 [get_ports {JC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] +##Sch name = JC9 +#set_property PACKAGE_PIN P17 [get_ports {JC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] +##Sch name = JC10 +#set_property PACKAGE_PIN R18 [get_ports {JC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + +##Pmod Header JXADC +##Sch name = XA1_P +#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] +##Sch name = XA2_P +#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] +##Sch name = XA3_P +#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] +##Sch name = XA4_P +#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] +##Sch name = XA1_N +#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] +##Sch name = XA2_N +#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] +##Sch name = XA3_N +#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] +##Sch name = XA4_N +#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] + + + +##VGA Connector +#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] +#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] +#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] +#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] +#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] +#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] +#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] +#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] +#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] +#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] +#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] +#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] +#set_property PACKAGE_PIN P19 [get_ports Hsync] + #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] +#set_property PACKAGE_PIN R19 [get_ports Vsync] + #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] + + +##USB-RS232 Interface +#set_property PACKAGE_PIN B18 [get_ports RsRx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] +#set_property PACKAGE_PIN A18 [get_ports RsTx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] + + +##USB HID (PS/2) +#set_property PACKAGE_PIN C17 [get_ports PS2Clk] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] + #set_property PULLUP true [get_ports PS2Clk] +#set_property PACKAGE_PIN B17 [get_ports PS2Data] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] + #set_property PULLUP true [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] +#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] +#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] +#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] +#set_property PACKAGE_PIN K19 [get_ports QspiCSn] + #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] + diff --git a/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd b/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd new file mode 100644 index 0000000000000000000000000000000000000000..d82ac16d121ed29c53f29281b5a0fbeb2879811a --- /dev/null +++ b/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd @@ -0,0 +1,73 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/22/2025 04:41:36 PM +-- Design Name: +-- Module Name: Enable190 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +use IEEE.STD_LOGIC_unsigned.ALL; + +entity clkdiv is + +Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + E190, clk190 : out STD_LOGIC); + +end clkdiv; + +architecture clkdiv of clkdiv is + +signal clkin: std_logic :='0'; + +begin + +--clock divider + + process(clk,reset) + variable q: std_logic_vector(23 downto 0):= X"000000"; + begin + + if reset ='1' then + q := X"000000"; + clkin <= '0'; + elsif clk'event and clk = '1' then + q := q+1; + if Q(18)='1' and clkin='0' then + E190 <= '1'; + else + E190 <= '0'; + end if; + + end if; + + clkin<= Q(18); + + end process; + + clk190 <= clkin; +end clkdiv; + diff --git a/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd b/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd new file mode 100644 index 0000000000000000000000000000000000000000..6200209bec22acc236cef0241ae2f024bf645c0f --- /dev/null +++ b/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd @@ -0,0 +1,69 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04/22/2025 03:05:23 PM +-- Design Name: +-- Module Name: anti_rebond - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity anti_rebond is + Port ( inp : in STD_LOGIC; + E : in STD_LOGIC; + clk : in STD_LOGIC; + output : out STD_LOGIC + ); +end anti_rebond; + +architecture Behavioral of anti_rebond is + +-- signaux internes pour connecter les bascules +signal q_signals : STD_LOGIC_VECTOR(5 downto 0); +signal o_1 : std_logic; + +begin + + o_1 <= q_signals(0) and q_signals(1) and q_signals(2); + + SYNC : process(clk) + begin + if (rising_edge(clk)) then + if (E = '1') then + q_signals(0) <= inp; + q_signals(1) <= q_signals(0); + q_signals(2) <= q_signals(1); + end if; + + q_signals(3) <= o_1; + q_signals(4) <= q_signals(3); + q_signals(5) <= q_signals(4); + end if; + end process; + + output <= q_signals(3) and q_signals(4) and (not q_signals(5)); + +end Behavioral; diff --git a/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd b/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd new file mode 100644 index 0000000000000000000000000000000000000000..ba5070ffa02ba865dfc938c6e557b8a8fc4a5359 --- /dev/null +++ b/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd @@ -0,0 +1,200 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14.04.2025 17:27:19 +-- Design Name: +-- Module Name: digi_code - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity digi_code is + Port ( btnC : in STD_LOGIC; -- reset + btnL : in STD_LOGIC; -- btn0 + btnD : in STD_LOGIC; -- btn1 + btnR : in STD_LOGIC; -- btn2 + btnU : in STD_LOGIC; -- btn3 + sw : in STD_LOGIC_VECTOR (7 downto 0); + clk : in STD_LOGIC; + led : out STD_LOGIC_VECTOR (1 downto 0)); +end digi_code; + +architecture Behavioral of digi_code is + + component anti_rebond + Port ( inp : in STD_LOGIC; + E : in STD_LOGIC; + clk : in STD_LOGIC; + output : out STD_LOGIC + ); + end component; + + + component clkdiv + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + E190, clk190 : out STD_LOGIC); + end component; + +-- Déclaration des états +type state_type is ( + S0, -- attente 1ère touche + S1, -- 1ère touche correcte + S2, -- 2ème touche correcte + S3, -- 3ème touche correcte + OPEND -- code correct +); + +signal state, next_state : state_type; +signal btn_value : std_logic_vector(1 downto 0); +signal E190, clk190 : std_logic; +signal btnR_pulse, btnL_pulse, btnU_pulse, btnD_pulse, btnC_pulse : std_logic; +begin + + clk_divide : clkdiv port map ( + clk => clk, + reset => open, + clk190 => clk190, + E190 => E190 + ); + + btn2_pulse : anti_rebond port map ( + inp => btnL, + E => E190, + clk => clk, + output => btnL_pulse + ); + + btn1_pulse : anti_rebond port map ( + inp => btnL, + E => E190, + clk => clk, + output => btnD_pulse + ); + + btn3_pulse : anti_rebond port map ( + inp => btnL, + E => E190, + clk => clk, + output => btnU_pulse + ); + + btn0_pulse : anti_rebond port map ( + inp => btnL, + E => E190, + clk => clk, + output => btnR_pulse + ); + + SYNC_PROC : process(clk) + begin + if rising_edge(clk) then + if btnC = '1' then + state <= S0; + else + state <= next_state; + end if; + end if; + end process; + + OUTPUT_DECODE : process(state) + begin + case state is + when S1 | S2 | S3 => + led(0) <= '1'; + led(1) <= '0'; + when S0 => + led <= "00"; + when OPEND => + led(0) <= '0'; + led(1) <= '1'; + end case; + end process; + + -- Encodage du bouton appuyé + process(btnL, btnD, btnR, btnU) + variable pressed_count : integer := 0; + begin + pressed_count := 0; + if btnL = '1' then pressed_count := pressed_count + 1; end if; + if btnD = '1' then pressed_count := pressed_count + 1; end if; + if btnR = '1' then pressed_count := pressed_count + 1; end if; + if btnU = '1' then pressed_count := pressed_count + 1; end if; + + if pressed_count = 1 then + if btnL = '1' then + btn_value <= "10"; + elsif btnD = '1' then + btn_value <= "01"; + elsif btnR = '1' then + btn_value <= "00"; + elsif btnU = '1' then + btn_value <= "11"; + end if; + else + btn_value <= "ZZ"; -- ou une autre valeur spéciale pour indiquer un cas invalide + end if; + end process; + + NEXT_STATE_DECODE : process(state, btn_value) + begin + next_state <= state; -- par défaut + case state is + when S0 => + if btn_value = sw(1 downto 0) then + next_state <= S1; + else + next_state <= S0; -- Mauvaise touche : reset de la séquence + end if; + when S1 => + if btn_value = sw(3 downto 2) then + next_state <= S2; + else + next_state <= S0; -- Mauvaise touche : reset de la séquence + end if; + when S2 => + if btn_value = sw(5 downto 4) then + next_state <= S3; + else + next_state <= S0; -- Mauvaise touche : reset de la séquence + end if; + when S3 => + if btn_value = sw(7 downto 6) then + next_state <= OPEND; + else + next_state <= S0; -- Mauvaise touche : reset de la séquence + end if; + when OPEND => + if btnC = '1' then + next_state <= S0; + end if; + + when others => + next_state <= state; + end case; + end process; + +end Behavioral; diff --git a/tp5_n/tp5_n.xpr b/tp5_n/tp5_n.xpr new file mode 100644 index 0000000000000000000000000000000000000000..fcd5dd1f9653912bbf7879f8e0c182bcdf1a6a0b --- /dev/null +++ b/tp5_n/tp5_n.xpr @@ -0,0 +1,241 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2021.1 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. --> + +<Project Version="7" Minor="55" Path="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.xpr"> + <DefaultLaunch Dir="$PRUNDIR"/> + <Configuration> + <Option Name="Id" Val="5e5d1ac8df47476c870b4cf306020630"/> + <Option Name="Part" Val="xc7a35tcpg236-1"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="CompiledLibDirXSim" Val=""/> + <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> + <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> + <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/> + <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> + <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> + <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> + <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> + <Option Name="SimulatorInstallDirModelSim" Val=""/> + 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