diff --git a/tp5_n/tp5_n.cache/wt/webtalk_pa.xml b/tp5_n/tp5_n.cache/wt/webtalk_pa.xml
index ef8b99bb9f675d855786e60faccf246a9eafd412..92d35065950e0d5bf53333508d8a29707fce589c 100644
--- a/tp5_n/tp5_n.cache/wt/webtalk_pa.xml
+++ b/tp5_n/tp5_n.cache/wt/webtalk_pa.xml
@@ -3,10 +3,10 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Tue Apr 22 17:36:36 2025">
+<application name="pa" timeStamp="Tue Apr 29 11:00:56 2025">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="1b11cba828a44658b54f60d00c70dab6" type="ProjectID"/>
-<property name="ProjectIteration" value="44" type="ProjectIteration"/>
+<property name="ProjectIteration" value="62" type="ProjectIteration"/>
 </section>
 <section name="PlanAhead Usage" visible="true">
 <item name="Project Data">
@@ -97,11 +97,6 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="TaskBanner_CLOSE" value="3" type="GuiHandlerData"/>
 <property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="27" type="GuiHandlerData"/>
 </item>
-<item name="Other">
-<property name="GuiMode" value="10" type="GuiMode"/>
-<property name="BatchMode" value="0" type="BatchMode"/>
-<property name="TclMode" value="6" type="TclMode"/>
-</item>
 </section>
 </application>
 </document>
diff --git a/tp5_n/tp5_n.hw/hw_1/hw.xml b/tp5_n/tp5_n.hw/hw_1/hw.xml
index 6e1f7774a44fb3e28e88df05be7836e0e04f2326..5678cb88109f23f08c9f2f4dddd9b85779e487e0 100644
--- a/tp5_n/tp5_n.hw/hw_1/hw.xml
+++ b/tp5_n/tp5_n.hw/hw_1/hw.xml
@@ -1,7 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2021.1 (64-bit)                     -->
-<!--                                                              -->
-<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.        -->
+<!-- Product Version: Vivado v2024.2 (64-bit)                                     -->
+<!--                                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                        -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.        -->
 
 <hwsession version="1" minor="2">
   <device name="xc7a35t_0" gui_info=""/>
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_15.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_15.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_15.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_16.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_16.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_16.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_17.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_17.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_17.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_18.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_18.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_18.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_19.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_19.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_19.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_20.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_20.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_20.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_21.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_21.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b154966b87a78f8a01933754495d58f0456077f5
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_21.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_22.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_22.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_22.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_23.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_23.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_23.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_24.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_24.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_24.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_25.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_25.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_25.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_26.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_26.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_26.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_27.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_27.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b154966b87a78f8a01933754495d58f0456077f5
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_27.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_28.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_28.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b154966b87a78f8a01933754495d58f0456077f5
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_28.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_29.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_29.xml
new file mode 100644
index 0000000000000000000000000000000000000000..fe8c56d9684b971a12ff5b8e28feb462c6440df9
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_29.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_30.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_30.xml
new file mode 100644
index 0000000000000000000000000000000000000000..a2825e7cd40ac7effcbd524a94a1a87e478c4a94
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_30.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_31.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_31.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b154966b87a78f8a01933754495d58f0456077f5
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_31.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_32.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_32.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_32.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/.jobs/vrs_config_33.xml b/tp5_n/tp5_n.runs/.jobs/vrs_config_33.xml
new file mode 100644
index 0000000000000000000000000000000000000000..09fdf53882b3f8b730bd125838d07caef429cc0a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/.jobs/vrs_config_33.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp5_n/tp5_n.runs/impl_1/clockInfo.txt b/tp5_n/tp5_n.runs/impl_1/clockInfo.txt
new file mode 100644
index 0000000000000000000000000000000000000000..d430dc2333c876eb4798b495280c4cfc31f8b51e
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/clockInfo.txt
@@ -0,0 +1,10 @@
+-------------------------------------
+| Tool Version : Vivado v.2024.2
+| Date         : Tue Apr 29 11:03:13 2025
+| Host         : LAPTOP-RU5MPQFG
+| Design       : design_1
+| Device       : xc7a35t-cpg236-1--
+-------------------------------------
+
+For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
+
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code.tcl b/tp5_n/tp5_n.runs/impl_1/digi_code.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5c479ded3128cf5aeba0c56bbd923b459ac6e620
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code.tcl
@@ -0,0 +1,310 @@
+namespace eval ::optrace {
+  variable script "C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code.tcl"
+  variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+  namespace eval ::dispatch {
+    variable connected false
+    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+      set result "true"
+      if {[catch {
+        if {[lsearch -exact [package names] DispatchTcl] < 0} {
+          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
+        }
+        if {$result eq "false"} {
+          puts "WARNING: Could not load dispatch client library"
+        }
+        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+        if { $connect_id eq "" } {
+          puts "WARNING: Could not initialize dispatch client"
+        } else {
+          puts "INFO: Dispatch client connection id - $connect_id"
+          set connected true
+        }
+      } catch_res]} {
+        puts "WARNING: failed to connect to dispatch server - $catch_res"
+      }
+    }
+  }
+}
+if {$::dispatch::connected} {
+  # Remove the dummy proc if it exists.
+  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+    rename ::OPTRACE ""
+  }
+  proc ::OPTRACE { task action {tags {} } } {
+    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+  }
+  # dispatch is generic. We specifically want to attach logging.
+  ::vitis_log::connect_client
+} else {
+  # Add dummy proc if it doesn't exist.
+  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+        # Do nothing
+    }
+  }
+}
+
+proc start_step { step } {
+  set stopFile ".stop.rst"
+  if {[file isfile .stop.rst]} {
+    puts ""
+    puts "*** Halting run - EA reset detected ***"
+    puts ""
+    puts ""
+    return -code error
+  }
+  set beginFile ".$step.begin.rst"
+  set platform "$::tcl_platform(platform)"
+  set user "$::tcl_platform(user)"
+  set pid [pid]
+  set host ""
+  if { [string equal $platform unix] } {
+    if { [info exist ::env(HOSTNAME)] } {
+      set host $::env(HOSTNAME)
+    } elseif { [info exist ::env(HOST)] } {
+      set host $::env(HOST)
+    }
+  } else {
+    if { [info exist ::env(COMPUTERNAME)] } {
+      set host $::env(COMPUTERNAME)
+    }
+  }
+  set ch [open $beginFile w]
+  puts $ch "<?xml version=\"1.0\"?>"
+  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+  puts $ch "    </Process>"
+  puts $ch "</ProcessHandle>"
+  close $ch
+}
+
+proc end_step { step } {
+  set endFile ".$step.end.rst"
+  set ch [open $endFile w]
+  close $ch
+}
+
+proc step_failed { step } {
+  set endFile ".$step.error.rst"
+  set ch [open $endFile w]
+  close $ch
+OPTRACE "impl_1" END { }
+}
+
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+  create_msg_db init_design.pb
+  set_param chipscope.maxJobs 3
+  set_param xicom.use_bs_reader 1
+  set_param runs.launchOptions { -jobs 6  }
+OPTRACE "create in-memory project" START { }
+  create_project -in_memory -part xc7a35tcpg236-1
+  set_property design_mode GateLvl [current_fileset]
+  set_param project.singleFileAddWarning.threshold 0
+OPTRACE "create in-memory project" END { }
+OPTRACE "set parameters" START { }
+  set_property webtalk.parent_dir C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.cache/wt [current_project]
+  set_property parent.project_path C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.xpr [current_project]
+  set_property ip_output_repo C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.cache/ip [current_project]
+  set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "set parameters" END { }
+OPTRACE "add files" START { }
+  add_files -quiet C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1/digi_code.dcp
+OPTRACE "read constraints: implementation" START { }
+  read_xdc C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc
+OPTRACE "read constraints: implementation" END { }
+OPTRACE "read constraints: implementation_pre" START { }
+OPTRACE "read constraints: implementation_pre" END { }
+OPTRACE "add files" END { }
+OPTRACE "link_design" START { }
+  link_design -top digi_code -part xc7a35tcpg236-1 
+OPTRACE "link_design" END { }
+OPTRACE "gray box cells" START { }
+OPTRACE "gray box cells" END { }
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+OPTRACE "init_design_write_hwdef" END { }
+  close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+  step_failed init_design
+  return -code error $RESULT
+} else {
+  end_step init_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+  create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+  opt_design 
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "opt_design reports" START { REPORT }
+  set_param project.isImplRun true
+  generate_parallel_reports -reports { "report_drc -file digi_code_drc_opted.rpt -pb digi_code_drc_opted.pb -rpx digi_code_drc_opted.rpx"  }
+  set_param project.isImplRun false
+OPTRACE "opt_design reports" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force digi_code_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+  close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+  step_failed opt_design
+  return -code error $RESULT
+} else {
+  end_step opt_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+  create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+  if { [llength [get_debug_cores -quiet] ] > 0 }  { 
+OPTRACE "implement_debug_core" START { }
+    implement_debug_core 
+OPTRACE "implement_debug_core" END { }
+  } 
+OPTRACE "place_design" START { }
+  place_design 
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "place_design reports" START { REPORT }
+  set_param project.isImplRun true
+  generate_parallel_reports -reports { "report_io -file digi_code_io_placed.rpt" "report_utilization -file digi_code_utilization_placed.rpt -pb digi_code_utilization_placed.pb" "report_control_sets -verbose -file digi_code_control_sets_placed.rpt"  }
+  set_param project.isImplRun false
+OPTRACE "place_design reports" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force digi_code_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+  close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+  step_failed place_design
+  return -code error $RESULT
+} else {
+  end_step place_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
+start_step phys_opt_design
+set ACTIVE_STEP phys_opt_design
+set rc [catch {
+  create_msg_db phys_opt_design.pb
+OPTRACE "read constraints: phys_opt_design" START { }
+OPTRACE "read constraints: phys_opt_design" END { }
+OPTRACE "phys_opt_design" START { }
+  phys_opt_design 
+OPTRACE "phys_opt_design" END { }
+OPTRACE "read constraints: phys_opt_design_post" START { }
+OPTRACE "read constraints: phys_opt_design_post" END { }
+OPTRACE "phys_opt_design report" START { REPORT }
+OPTRACE "phys_opt_design report" END { }
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force digi_code_physopt.dcp
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
+  close_msg_db -file phys_opt_design.pb
+} RESULT]
+if {$rc} {
+  step_failed phys_opt_design
+  return -code error $RESULT
+} else {
+  end_step phys_opt_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Physical Opt Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+  create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+  route_design 
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "route_design reports" START { REPORT }
+  set_param project.isImplRun true
+  generate_parallel_reports -reports { "report_drc -file digi_code_drc_routed.rpt -pb digi_code_drc_routed.pb -rpx digi_code_drc_routed.rpx" "report_methodology -file digi_code_methodology_drc_routed.rpt -pb digi_code_methodology_drc_routed.pb -rpx digi_code_methodology_drc_routed.rpx" "report_power -file digi_code_power_routed.rpt -pb digi_code_power_summary_routed.pb -rpx digi_code_power_routed.rpx" "report_route_status -file digi_code_route_status.rpt -pb digi_code_route_status.pb" "report_timing_summary -max_paths 10 -report_unconstrained -file digi_code_timing_summary_routed.rpt -pb digi_code_timing_summary_routed.pb -rpx digi_code_timing_summary_routed.rpx -warn_on_violation " "report_incremental_reuse -file digi_code_incremental_reuse_routed.rpt" "report_clock_utilization -file digi_code_clock_utilization_routed.rpt" "report_bus_skew -warn_on_violation -file digi_code_bus_skew_routed.rpt -pb digi_code_bus_skew_routed.pb -rpx digi_code_bus_skew_routed.rpx"  }
+  set_param project.isImplRun false
+OPTRACE "route_design reports" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force digi_code_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design misc" START { }
+  close_msg_db -file route_design.pb
+} RESULT]
+if {$rc} {
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+  write_checkpoint -force digi_code_routed_error.dcp
+  step_failed route_design
+  return -code error $RESULT
+} else {
+  end_step route_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+  create_msg_db write_bitstream.pb
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+  catch { write_mem_info -force -no_partial_mmi digi_code.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+  write_bitstream -force digi_code.bit 
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+  catch {write_debug_probes -quiet -force digi_code}
+  catch {file copy -force digi_code.ltx debug_nets.ltx}
+  close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+  step_failed write_bitstream
+  return -code error $RESULT
+} else {
+  end_step write_bitstream
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code.vdi b/tp5_n/tp5_n.runs/impl_1/digi_code.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..94aebc975903721eb013c1613bde8fc3737e6142
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code.vdi
@@ -0,0 +1,738 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Apr 29 11:02:11 2025
+# Process ID         : 18068
+# Current directory  : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1
+# Command line       : vivado.exe -log digi_code.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source digi_code.tcl -notrace
+# Log file           : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code.vdi
+# Journal file       : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1\vivado.jou
+# Running On         : LAPTOP-RU5MPQFG
+# Platform           : Windows Server 2016 or Windows 10
+# Operating System   : 26100
+# Processor Detail   : AMD Ryzen 5 5500U with Radeon Graphics         
+# CPU Frequency      : 2096 MHz
+# CPU Physical cores : 6
+# CPU Logical cores  : 12
+# Host memory        : 16468 MB
+# Swap memory        : 1073 MB
+# Total Virtual      : 17542 MB
+# Available Virtual  : 8793 MB
+#-----------------------------------------------------------
+source digi_code.tcl -notrace
+Command: link_design -top digi_code -part xc7a35tcpg236-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 530.750 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+Finished Parsing XDC File [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 666.465 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 671.504 ; gain = 341.914
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 706.367 ; gain = 34.863
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 2231fd2ba
+
+Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1239.883 ; gain = 533.516
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 2231fd2ba
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2231fd2ba
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 1 Initialization | Checksum: 2231fd2ba
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 2231fd2ba
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 2231fd2ba
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 2 Timer Update And Timing Data Collection | Checksum: 2231fd2ba
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 3 Retarget
+INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 2231fd2ba
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Retarget | Checksum: 2231fd2ba
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 2231fd2ba
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Constant propagation | Checksum: 2231fd2ba
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
+Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 5 Sweep | Checksum: 225e996f8
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Sweep | Checksum: 225e996f8
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 225e996f8
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 1642.617 ; gain = 0.000
+BUFG optimization | Checksum: 225e996f8
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 225e996f8
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.157 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Shift Register Optimization | Checksum: 225e996f8
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 225e996f8
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.160 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Post Processing Netlist | Checksum: 225e996f8
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 20bc84239
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.171 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 20bc84239
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.190 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 9 Finalization | Checksum: 20bc84239
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.190 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               0  |                                              0  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 20bc84239
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.194 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 20bc84239
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 20bc84239
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Ending Netlist Obfuscation Task | Checksum: 20bc84239
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1642.617 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1642.617 ; gain = 971.113
+INFO: [Vivado 12-24828] Executing command : report_drc -file digi_code_drc_opted.rpt -pb digi_code_drc_opted.pb -rpx digi_code_drc_opted.rpx
+Command: report_drc -file digi_code_drc_opted.rpt -pb digi_code_drc_opted.pb -rpx digi_code_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2024.2/data/ip'.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_drc_opted.rpt.
+report_drc completed successfully
+report_drc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1642.617 ; gain = 0.000
+generate_parallel_reports: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1642.617 ; gain = 0.000
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.089 . Memory (MB): peak = 1642.617 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1be5a719a
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 218c413a4
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.405 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 232fe8f25
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.655 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 232fe8f25
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.659 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 1 Placer Initialization | Checksum: 232fe8f25
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.663 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 2e97ed90a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.853 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 21a1232ee
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 21a1232ee
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 2.4 Global Place Phase1
+Phase 2.4 Global Place Phase1 | Checksum: 30009ddef
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 2.5 Global Place Phase2
+
+Phase 2.5.1 UpdateTiming Before Physical Synthesis
+Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 2c8dce0dc
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 2.5.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 0 net or LUT. Breaked 0 LUT, combined 0 existing LUT and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+|  LUT Combining                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  Total                                            |            0  |              0  |                     0  |           0  |           4  |  00:00:00  |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.5.2 Physical Synthesis In Placer | Checksum: 2c8dce0dc
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 2.5 Global Place Phase2 | Checksum: 2ec4b11dc
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 2 Global Placement | Checksum: 2ec4b11dc
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 2860d9432
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 28de019f0
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 23c6d2336
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 25fd38fc2
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 3208911b9
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 2f55865ee
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 2d1c2d962
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 3 Detail Placement | Checksum: 2d1c2d962
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 2b91db27a
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=6.639 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 1ac08182c
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1642.617 ; gain = 0.000
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 22a243515
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 4.1.1.1 BUFG Insertion | Checksum: 2b91db27a
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=6.639. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 2452bf53e
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 4.1 Post Commit Optimization | Checksum: 2452bf53e
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 2452bf53e
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 2452bf53e
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 4.3 Placer Reporting | Checksum: 2452bf53e
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1642.617 ; gain = 0.000
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 28d4b454b
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Ending Placer Task | Checksum: 224d5b483
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1642.617 ; gain = 0.000
+63 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1642.617 ; gain = 0.000
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 2 threads.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file digi_code_utilization_placed.rpt -pb digi_code_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file digi_code_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.109 . Memory (MB): peak = 1642.617 ; gain = 0.000
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file digi_code_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1642.617 ; gain = 0.000
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1642.617 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.102 . Memory (MB): peak = 1642.617 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_placed.dcp' has been generated.
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1649.984 ; gain = 7.367
+INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 6.639 | TNS= 0.000 | 
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1667.875 ; gain = 0.059
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1667.875 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1667.875 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1667.875 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1667.875 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1667.875 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1667.875 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: ba020e96 ConstDB: 0 ShapeSum: ca524996 RouteDB: a0815c57
+Post Restoration Checksum: NetGraph: ffa25798 | NumContArr: 1b51fee6 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 2a0464bb8
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:49 . Memory (MB): peak = 1755.539 ; gain = 86.738
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 2a0464bb8
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:49 . Memory (MB): peak = 1755.539 ; gain = 86.738
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 2a0464bb8
+
+Time (s): cpu = 00:00:51 ; elapsed = 00:00:49 . Memory (MB): peak = 1755.539 ; gain = 86.738
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 23ea06d19
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:49 . Memory (MB): peak = 1784.711 ; gain = 115.910
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.580  | TNS=0.000  | WHS=-0.142 | THS=-1.624 |
+
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0 %
+  Global Horizontal Routing Utilization  = 0 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 85
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 85
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: 1a2dc0cd5
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 1a2dc0cd5
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 1d8b6f05b
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+Phase 4 Initial Routing | Checksum: 1d8b6f05b
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.286  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 5.1 Global Iteration 0 | Checksum: 2b4a38a9a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+Phase 5 Rip-up And Reroute | Checksum: 2b4a38a9a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 2b4a38a9a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 2b4a38a9a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+Phase 6 Delay and Skew Optimization | Checksum: 2b4a38a9a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.379  | TNS=0.000  | WHS=0.117  | THS=0.000  |
+
+Phase 7.1 Hold Fix Iter | Checksum: 2b498ddb5
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+Phase 7 Post Hold Fix | Checksum: 2b498ddb5
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.0102846 %
+  Global Horizontal Routing Utilization  = 0.0113222 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 8 Route finalize | Checksum: 2b498ddb5
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 2b498ddb5
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 34e38afb7
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 34e38afb7
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=6.379  | TNS=0.000  | WHS=0.117  | THS=0.000  |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 34e38afb7
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+Total Elapsed time in route_design: 50.004 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 16de45260
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 16de45260
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 115.910
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+85 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:53 ; elapsed = 00:00:50 . Memory (MB): peak = 1784.711 ; gain = 116.836
+INFO: [Vivado 12-24828] Executing command : report_drc -file digi_code_drc_routed.rpt -pb digi_code_drc_routed.pb -rpx digi_code_drc_routed.rpx
+Command: report_drc -file digi_code_drc_routed.rpt -pb digi_code_drc_routed.pb -rpx digi_code_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_drc_routed.rpt.
+report_drc completed successfully
+report_drc: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 1815.371 ; gain = 30.660
+INFO: [Vivado 12-24828] Executing command : report_methodology -file digi_code_methodology_drc_routed.rpt -pb digi_code_methodology_drc_routed.pb -rpx digi_code_methodology_drc_routed.rpx
+Command: report_methodology -file digi_code_methodology_drc_routed.rpt -pb digi_code_methodology_drc_routed.pb -rpx digi_code_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_methodology_drc_routed.rpt.
+report_methodology completed successfully
+report_drc: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1831.285 ; gain = 15.914
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file digi_code_timing_summary_routed.rpt -pb digi_code_timing_summary_routed.pb -rpx digi_code_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 2 threads.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file digi_code_route_status.rpt -pb digi_code_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file digi_code_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_power -file digi_code_power_routed.rpt -pb digi_code_power_summary_routed.pb -rpx digi_code_power_routed.rpx
+Command: report_power -file digi_code_power_routed.rpt -pb digi_code_power_summary_routed.pb -rpx digi_code_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+102 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file digi_code_clock_utilization_routed.rpt
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file digi_code_bus_skew_routed.rpt -pb digi_code_bus_skew_routed.pb -rpx digi_code_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+generate_parallel_reports: Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 1838.199 ; gain = 53.488
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1838.199 ; gain = 0.000
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1838.199 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1838.199 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1838.199 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1838.199 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1838.199 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.111 . Memory (MB): peak = 1838.199 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_routed.dcp' has been generated.
+Command: write_bitstream -force digi_code.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado 12-3199] DRC finished with 0 Errors
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./digi_code.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
+INFO: [Common 17-83] Releasing license: Implementation
+117 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:30 ; elapsed = 00:02:10 . Memory (MB): peak = 2304.281 ; gain = 466.082
+INFO: [Common 17-206] Exiting Vivado at Tue Apr 29 11:06:33 2025...
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_2948.backup.vdi b/tp5_n/tp5_n.runs/impl_1/digi_code_2948.backup.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..1785710fa2315544b5ad1e47d9cde9a536dcbe50
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_2948.backup.vdi
@@ -0,0 +1,718 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Apr 29 08:54:05 2025
+# Process ID         : 2948
+# Current directory  : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1
+# Command line       : vivado.exe -log digi_code.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source digi_code.tcl -notrace
+# Log file           : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code.vdi
+# Journal file       : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1\vivado.jou
+# Running On         : LAPTOP-RU5MPQFG
+# Platform           : Windows Server 2016 or Windows 10
+# Operating System   : 26100
+# Processor Detail   : AMD Ryzen 5 5500U with Radeon Graphics         
+# CPU Frequency      : 2096 MHz
+# CPU Physical cores : 6
+# CPU Logical cores  : 12
+# Host memory        : 16468 MB
+# Swap memory        : 1073 MB
+# Total Virtual      : 17542 MB
+# Available Virtual  : 9038 MB
+#-----------------------------------------------------------
+source digi_code.tcl -notrace
+Command: link_design -top digi_code -part xc7a35tcpg236-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 531.191 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+Finished Parsing XDC File [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 666.527 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 670.500 ; gain = 341.133
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 709.297 ; gain = 38.797
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 1d0bf465f
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1247.191 ; gain = 537.895
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 1d0bf465f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1d0bf465f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 1 Initialization | Checksum: 1d0bf465f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 1d0bf465f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 1d0bf465f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 2 Timer Update And Timing Data Collection | Checksum: 1d0bf465f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 3 Retarget
+INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 1d0bf465f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Retarget | Checksum: 1d0bf465f
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 1d0bf465f
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Constant propagation | Checksum: 1d0bf465f
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
+Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 5 Sweep | Checksum: 1de018a19
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Sweep | Checksum: 1de018a19
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 1de018a19
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.110 . Memory (MB): peak = 1651.219 ; gain = 0.000
+BUFG optimization | Checksum: 1de018a19
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 1de018a19
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.113 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Shift Register Optimization | Checksum: 1de018a19
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 1de018a19
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.115 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Post Processing Netlist | Checksum: 1de018a19
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1f88bc128
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.120 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 1f88bc128
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 9 Finalization | Checksum: 1f88bc128
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               0  |                                              0  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 1f88bc128
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.135 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 1f88bc128
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 1f88bc128
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Ending Netlist Obfuscation Task | Checksum: 1f88bc128
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1651.219 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1651.219 ; gain = 980.719
+INFO: [Vivado 12-24828] Executing command : report_drc -file digi_code_drc_opted.rpt -pb digi_code_drc_opted.pb -rpx digi_code_drc_opted.rpx
+Command: report_drc -file digi_code_drc_opted.rpt -pb digi_code_drc_opted.pb -rpx digi_code_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2024.2/data/ip'.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1651.219 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15e03273b
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1907acdbc
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.243 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1afc5aa02
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.444 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1afc5aa02
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.450 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 1 Placer Initialization | Checksum: 1afc5aa02
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.466 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 23c73cd73
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.593 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1d07e748a
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.675 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 1d07e748a
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.678 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 2.4 Global Place Phase1
+Phase 2.4 Global Place Phase1 | Checksum: 21bd3a702
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 2.5 Global Place Phase2
+
+Phase 2.5.1 UpdateTiming Before Physical Synthesis
+Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 20015bbb8
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 2.5.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 0 net or LUT. Breaked 0 LUT, combined 0 existing LUT and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+|  LUT Combining                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  Total                                            |            0  |              0  |                     0  |           0  |           4  |  00:00:00  |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.5.2 Physical Synthesis In Placer | Checksum: 20015bbb8
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 2.5 Global Place Phase2 | Checksum: 25f16da73
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 2 Global Placement | Checksum: 25f16da73
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 232dbb870
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17059b12e
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 217e2cd6b
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 196516d53
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 27f536da0
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 24f74e474
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 1a8e0441c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 3 Detail Placement | Checksum: 1a8e0441c
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 13d4e746d
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=6.525 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: e70699b7
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1651.219 ; gain = 0.000
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 1b2b72c80
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 4.1.1.1 BUFG Insertion | Checksum: 13d4e746d
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=6.525. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1815bc1b8
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 4.1 Post Commit Optimization | Checksum: 1815bc1b8
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1815bc1b8
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1815bc1b8
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 4.3 Placer Reporting | Checksum: 1815bc1b8
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e7facb8d
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Ending Placer Task | Checksum: 17ecd9c68
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1651.219 ; gain = 0.000
+63 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 2 threads.
+INFO: [Vivado 12-24828] Executing command : report_io -file digi_code_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1651.219 ; gain = 0.000
+INFO: [Vivado 12-24828] Executing command : report_utilization -file digi_code_utilization_placed.rpt -pb digi_code_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file digi_code_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1651.219 ; gain = 0.000
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1651.219 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1651.219 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_placed.dcp' has been generated.
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1661.035 ; gain = 9.816
+INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 6.525 | TNS= 0.000 | 
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1678.887 ; gain = 0.000
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1678.887 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1678.887 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1678.887 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1678.887 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1678.887 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1678.887 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 504f184c ConstDB: 0 ShapeSum: 8dfd27c5 RouteDB: a0815c57
+Post Restoration Checksum: NetGraph: ff887558 | NumContArr: 676a45a5 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 2ec44b037
+
+Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 1770.395 ; gain = 91.488
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 2ec44b037
+
+Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 1770.395 ; gain = 91.488
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 2ec44b037
+
+Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 1770.395 ; gain = 91.488
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 2dabcb73a
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.460  | TNS=0.000  | WHS=-0.095 | THS=-1.234 |
+
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0 %
+  Global Horizontal Routing Utilization  = 0 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 88
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 88
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: 2052bd68d
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 2052bd68d
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 2539a3e07
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+Phase 4 Initial Routing | Checksum: 2539a3e07
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.506  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 5.1 Global Iteration 0 | Checksum: 2ba7dc49d
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+Phase 5 Rip-up And Reroute | Checksum: 2ba7dc49d
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 2e9c96639
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.599  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 6.1 Delay CleanUp | Checksum: 2e9c96639
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 2e9c96639
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+Phase 6 Delay and Skew Optimization | Checksum: 2e9c96639
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.599  | TNS=0.000  | WHS=0.150  | THS=0.000  |
+
+Phase 7.1 Hold Fix Iter | Checksum: 281a1bffb
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+Phase 7 Post Hold Fix | Checksum: 281a1bffb
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.0110022 %
+  Global Horizontal Routing Utilization  = 0.0105414 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 8 Route finalize | Checksum: 281a1bffb
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 281a1bffb
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 27510274c
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 27510274c
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=6.599  | TNS=0.000  | WHS=0.150  | THS=0.000  |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 27510274c
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+Total Elapsed time in route_design: 21.246 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 162da814f
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 162da814f
+
+Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.371
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+86 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 1800.277 ; gain = 121.391
+INFO: [Vivado 12-24828] Executing command : report_drc -file digi_code_drc_routed.rpt -pb digi_code_drc_routed.pb -rpx digi_code_drc_routed.rpx
+Command: report_drc -file digi_code_drc_routed.rpt -pb digi_code_drc_routed.pb -rpx digi_code_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file digi_code_methodology_drc_routed.rpt -pb digi_code_methodology_drc_routed.pb -rpx digi_code_methodology_drc_routed.rpx
+Command: report_methodology -file digi_code_methodology_drc_routed.rpt -pb digi_code_methodology_drc_routed.pb -rpx digi_code_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file digi_code_timing_summary_routed.rpt -pb digi_code_timing_summary_routed.pb -rpx digi_code_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 2 threads.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file digi_code_route_status.rpt -pb digi_code_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file digi_code_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_power -file digi_code_power_routed.rpt -pb digi_code_power_summary_routed.pb -rpx digi_code_power_routed.rpx
+Command: report_power -file digi_code_power_routed.rpt -pb digi_code_power_summary_routed.pb -rpx digi_code_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+103 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file digi_code_clock_utilization_routed.rpt
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file digi_code_bus_skew_routed.rpt -pb digi_code_bus_skew_routed.pb -rpx digi_code_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+generate_parallel_reports: Time (s): cpu = 00:00:14 ; elapsed = 00:00:08 . Memory (MB): peak = 1862.355 ; gain = 62.078
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1862.355 ; gain = 0.000
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1862.355 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1862.355 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1862.355 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1862.355 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1862.355 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1862.355 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code_routed.dcp' has been generated.
+INFO: [Common 17-206] Exiting Vivado at Tue Apr 29 10:55:17 2025...
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_bus_skew_routed.pb b/tp5_n/tp5_n.runs/impl_1/digi_code_bus_skew_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/digi_code_bus_skew_routed.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_bus_skew_routed.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_bus_skew_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..09c21896f0f6a31a595f27ef6df33f2ad26240b6
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_bus_skew_routed.rpt
@@ -0,0 +1,16 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 11:04:22 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_bus_skew -warn_on_violation -file digi_code_bus_skew_routed.rpt -pb digi_code_bus_skew_routed.pb -rpx digi_code_bus_skew_routed.rpx
+| Design       : digi_code
+| Device       : 7a35t-cpg236
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_clock_utilization_routed.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_clock_utilization_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..7b46a59bce679d995a727fd7ddeb5abe9f84c783
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_clock_utilization_routed.rpt
@@ -0,0 +1,146 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 11:04:22 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_clock_utilization -file digi_code_clock_utilization_routed.rpt
+| Design       : digi_code
+| Device       : 7a35t-cpg236
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Clock Regions: Key Resource Utilization
+5. Clock Regions : Global Clock Summary
+6. Device Cell Placement Summary for Global Clock g0
+7. Clock Region Cell Placement per Global Clock: Region X0Y0
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type     | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL |    1 |        32 |   0 |            0 |      0 |
+| BUFH     |    0 |        72 |   0 |            0 |      0 |
+| BUFIO    |    0 |        20 |   0 |            0 |      0 |
+| BUFMR    |    0 |        10 |   0 |            0 |      0 |
+| BUFR     |    0 |        20 |   0 |            0 |      0 |
+| MMCM     |    0 |         5 |   0 |            0 |      0 |
+| PLL      |    0 |         5 |   0 |            0 |      0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site          | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock       | Driver Pin           | Net           |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
+| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y0 | n/a          |                 1 |          53 |               0 |       10.000 | sys_clk_pin | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site      | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin      | Net      |
++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
+| src0      | g0        | IBUF/O          | IOB_X1Y26  | IOB_X1Y26 | X1Y0         |           1 |               0 |              10.000 | sys_clk_pin  | clk_IBUF_inst/O | clk_IBUF |
++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+4. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   53 |  1200 |    9 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1500 |    0 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
+| X0Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1200 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1500 |    0 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
+| X0Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1800 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y2              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |   950 |    0 |   300 |    0 |    10 |    0 |     5 |    0 |    20 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+5. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+|    | X0 | X1 |
++----+----+----+
+| Y2 |  0 |  0 |
+| Y1 |  0 |  0 |
+| Y0 |  0 |  0 |
++----+----+----+
+
+
+6. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock       | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net           |
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
+| g0        | BUFG/O          | n/a               | sys_clk_pin |      10.000 | {0.000 5.000} |          53 |        0 |              0 |        0 | clk_IBUF_BUFG |
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+-----+----+-----------------------+
+|    | X0  | X1 | HORIZONTAL PROG DELAY |
++----+-----+----+-----------------------+
+| Y2 |   0 |  0 |                     - |
+| Y1 |   0 |  0 |                     - |
+| Y0 |  53 |  0 |                     0 |
++----+-----+----+-----------------------+
+
+
+7. Clock Region Cell Placement per Global Clock: Region X0Y0
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net           |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
+| g0        | n/a   | BUFG/O          | None       |          53 |               0 | 53 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | clk_IBUF_BUFG |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives 
+set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]
+
+# Location of IO Primitives which is load of clock spine
+
+# Location of clock ports
+set_property LOC IOB_X1Y26 [get_ports clk]
+
+# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
+#startgroup
+create_pblock {CLKAG_clk_IBUF_BUFG}
+add_cells_to_pblock [get_pblocks  {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
+resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}
+#endgroup
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_control_sets_placed.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_control_sets_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..7165a4d4c1d58c823b3a742220df03752d4decd0
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_control_sets_placed.rpt
@@ -0,0 +1,80 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 11:03:16 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_control_sets -verbose -file digi_code_control_sets_placed.rpt
+| Design       : digi_code
+| Device       : xc7a35t
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+|                          Status                          | Count |
++----------------------------------------------------------+-------+
+| Total control sets                                       |     2 |
+|    Minimum number of control sets                        |     2 |
+|    Addition due to synthesis replication                 |     0 |
+|    Addition due to physical synthesis replication        |     0 |
+| Unused register locations in slices containing registers |     3 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+|       Fanout       | Count |
++--------------------+-------+
+| Total control sets |     2 |
+| >= 0 to < 4        |     0 |
+| >= 4 to < 6        |     0 |
+| >= 6 to < 8        |     0 |
+| >= 8 to < 10       |     0 |
+| >= 10 to < 12      |     0 |
+| >= 12 to < 14      |     0 |
+| >= 14 to < 16      |     1 |
+| >= 16              |     1 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No           | No                    | No                     |              38 |            9 |
+| No           | No                    | Yes                    |               0 |            0 |
+| No           | Yes                   | No                     |               0 |            0 |
+| Yes          | No                    | No                     |              15 |            3 |
+| Yes          | No                    | Yes                    |               0 |            0 |
+| Yes          | Yes                   | No                     |               0 |            0 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++----------------+-----------------+------------------+------------------+----------------+--------------+
+|  Clock Signal  |  Enable Signal  | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++----------------+-----------------+------------------+------------------+----------------+--------------+
+|  clk_IBUF_BUFG | clk_divide/E[0] |                  |                3 |             15 |         5.00 |
+|  clk_IBUF_BUFG |                 |                  |                9 |             38 |         4.22 |
++----------------+-----------------+------------------+------------------+----------------+--------------+
+
+
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_drc_opted.pb b/tp5_n/tp5_n.runs/impl_1/digi_code_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/digi_code_drc_opted.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_drc_opted.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_drc_opted.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..c006cb4ba41a8c7a3e19973158c575166479cc50
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_drc_opted.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 11:03:07 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_drc -file digi_code_drc_opted.rpt -pb digi_code_drc_opted.pb -rpx digi_code_drc_opted.rpx
+| Design       : digi_code
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max checks: <unlimited>
+             Checks found: 1
++----------+----------+-----------------------------------------------------+--------+
+| Rule     | Severity | Description                                         | Checks |
++----------+----------+-----------------------------------------------------+--------+
+| CFGBVS-1 | Warning  | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1      |
++----------+----------+-----------------------------------------------------+--------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_drc_routed.pb b/tp5_n/tp5_n.runs/impl_1/digi_code_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..cb5bb3226dc0fb7cffeddb74a85bce825dc47e0a
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/digi_code_drc_routed.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_drc_routed.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..f400720ee2a067287d44726362aea3a80406488c
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_drc_routed.rpt
@@ -0,0 +1,61 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 11:04:15 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_drc -file digi_code_drc_routed.rpt -pb digi_code_drc_routed.pb -rpx digi_code_drc_routed.rpx
+| Design       : digi_code
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max checks: <unlimited>
+             Checks found: 3
++----------+----------+-----------------------------------------------------+--------+
+| Rule     | Severity | Description                                         | Checks |
++----------+----------+-----------------------------------------------------+--------+
+| CFGBVS-1 | Warning  | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1      |
+| PDRC-136 | Warning  | SLICE_PairEqSame_C6C5_WARN                          | 1      |
+| PDRC-138 | Warning  | SLICE_PairEqSame_D6D5_WARN                          | 1      |
++----------+----------+-----------------------------------------------------+--------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+PDRC-136#1 Warning
+SLICE_PairEqSame_C6C5_WARN  
+Luts C6LUT and C5LUT in use in site SLICE_X0Y13 with different equations without A6 pin connected to Global Logic High.
+Related violations: <none>
+
+PDRC-138#1 Warning
+SLICE_PairEqSame_D6D5_WARN  
+Luts D6LUT and D5LUT in use in site SLICE_X0Y13 with different equations without A6 pin connected to Global Logic High.
+Related violations: <none>
+
+
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_io_placed.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_io_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..d9ec6e9f1e8aaf35501a69803449d4080578409f
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_io_placed.rpt
@@ -0,0 +1,280 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version              : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date                      : Tue Apr 29 11:03:16 2025
+| Host                      : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command                   : report_io -file digi_code_io_placed.rpt
+| Design                    : digi_code
+| Device                    : xc7a35t
+| Speed File                : -1
+| Package                   : cpg236
+| Package Version           : FINAL 2014-02-19
+| Package Pin Delay Version : VERS. 2.0 2014-02-19
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+|            16 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type  | Pin Name                     | Use           | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A2         |             |            | MGTPTXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A4         |             |            | MGTPRXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A6         |             |            | MGTPRXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A8         |             |            | MGTREFCLK0N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A10        |             |            | MGTREFCLK1N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A11        |             | Dedicated  | DXP_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A12        |             | Dedicated  | VP_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A13        |             | Dedicated  | VREFN_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A14        |             | High Range | IO_L6P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A15        |             | High Range | IO_L6N_T0_VREF_16            | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A16        |             | High Range | IO_L12P_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A17        |             | High Range | IO_L12N_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A18        |             | High Range | IO_L19N_T3_VREF_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B1         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B2         |             |            | MGTPTXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B4         |             |            | MGTPRXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B6         |             |            | MGTPRXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B8         |             |            | MGTREFCLK0P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B10        |             |            | MGTREFCLK1P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B11        |             | Dedicated  | DXN_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B12        |             | Dedicated  | VREFP_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B13        |             | Dedicated  | VN_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B14        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B15        |             | High Range | IO_L11N_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B16        |             | High Range | IO_L13N_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B17        |             | High Range | IO_L14N_T2_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B18        |             | High Range | IO_L19P_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B19        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| C1         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C4         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C5         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C6         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C7         |             |            | MGTRREF_216                  | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C8         |             | Dedicated  | TCK_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C9         |             | Dedicated  | VCCBATT_0                    | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C10        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C11        |             | Dedicated  | CCLK_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C12        |             | Dedicated  | GNDADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C13        |             | Dedicated  | VCCADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C14        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| C15        |             | High Range | IO_L11P_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C16        |             | High Range | IO_L13P_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C17        |             | High Range | IO_L14P_T2_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C18        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| C19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D1         |             |            | MGTPTXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D2         |             |            | MGTPTXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D17        |             | High Range | IO_0_14                      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D18        |             | High Range | IO_L1P_T0_D00_MOSI_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D19        |             | High Range | IO_L1N_T0_D01_DIN_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E1         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E2         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E17        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E18        |             | High Range | IO_L3P_T0_DQS_PUDC_B_14      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E19        | led[1]      | High Range | IO_L3N_T0_DQS_EMCCLK_14      | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| F1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F3         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F17        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| F18        |             | High Range | IO_L2N_T0_D03_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G2         |             | High Range | IO_L1N_T0_AD4N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G3         |             | High Range | IO_L1P_T0_AD4P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G7         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G9         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G12        |             | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| G13        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| G17        |             | High Range | IO_L5N_T0_D07_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G18        |             | High Range | IO_L2P_T0_D02_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G19        |             | High Range | IO_L4N_T0_D05_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H1         |             | High Range | IO_L3P_T0_DQS_AD5P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H2         |             | High Range | IO_L2P_T0_AD12P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H3         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| H7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H9         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H13        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| H17        |             | High Range | IO_L5P_T0_D06_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H18        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H19        |             | High Range | IO_L4P_T0_D04_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J1         |             | High Range | IO_L3N_T0_DQS_AD5N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J2         |             | High Range | IO_L2N_T0_AD12N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J3         |             | High Range | IO_L7P_T1_AD6P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| J8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J13        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| J17        |             | High Range | IO_L7P_T1_D09_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J18        |             | High Range | IO_L7N_T1_D10_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J19        |             | High Range | IO_L6N_T0_D08_VREF_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K1         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| K2         |             | High Range | IO_L5P_T0_AD13P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K3         |             | High Range | IO_L7N_T1_AD6N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| K8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K12        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| K13        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| K17        |             | High Range | IO_L12N_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K18        |             | High Range | IO_L8N_T1_D12_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K19        |             | High Range | IO_L6P_T0_FCS_B_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L1         |             | High Range | IO_L6N_T0_VREF_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L2         |             | High Range | IO_L5N_T0_AD13N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L3         |             | High Range | IO_L8P_T1_AD14P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| L8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L12        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| L13        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| L17        |             | High Range | IO_L12P_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L18        |             | High Range | IO_L8P_T1_D11_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M1         |             | High Range | IO_L9N_T1_DQS_AD7N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M2         |             | High Range | IO_L9P_T1_DQS_AD7P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M3         |             | High Range | IO_L8N_T1_AD14N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| M8         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| M9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M11        |             |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M12        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| M13        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M17        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| M18        |             | High Range | IO_L11P_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M19        |             | High Range | IO_L11N_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N1         |             | High Range | IO_L10N_T1_AD15N_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N2         |             | High Range | IO_L10P_T1_AD15P_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N3         |             | High Range | IO_L12P_T1_MRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N7         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| N8         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| N9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N11        |             |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N13        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N17        |             | High Range | IO_L13P_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N18        |             | High Range | IO_L9P_T1_DQS_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N19        |             | High Range | IO_L9N_T1_DQS_D13_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P1         |             | High Range | IO_L19N_T3_VREF_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P3         |             | High Range | IO_L12N_T1_MRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P17        |             | High Range | IO_L13N_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P18        |             | High Range | IO_L14P_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P19        |             | High Range | IO_L10P_T1_D14_14            | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R1         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| R2         |             | High Range | IO_L1P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R3         |             | High Range | IO_L2P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R17        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| R18        |             | High Range | IO_L14N_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R19        |             | High Range | IO_L10N_T1_D15_14            | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T1         |             | High Range | IO_L3P_T0_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T2         |             | High Range | IO_L1N_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T3         |             | High Range | IO_L2N_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T17        | btnR        | High Range | IO_L17P_T2_A14_D30_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| T18        | btnU        | High Range | IO_L17N_T2_A13_D29_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| T19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U1         |             | High Range | IO_L3N_T0_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U2         |             | High Range | IO_L9N_T1_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U3         |             | High Range | IO_L9P_T1_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U4         |             | High Range | IO_L11P_T1_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U5         |             | High Range | IO_L16P_T2_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U6         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U7         |             | High Range | IO_L19P_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U8         |             | High Range | IO_L14P_T2_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U10        |             | Dedicated  | M2_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U11        |             | Dedicated  | INIT_B_0                     | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U12        |             | Dedicated  | DONE_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U13        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| U14        |             | High Range | IO_25_14                     | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U15        |             | High Range | IO_L23P_T3_A03_D19_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U16        | led[0]      | High Range | IO_L23N_T3_A02_D18_14        | OUTPUT        | LVCMOS33    |      14 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| U17        | btnD        | High Range | IO_L18P_T2_A12_D28_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| U18        | btnC        | High Range | IO_L18N_T2_A11_D27_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| U19        |             | High Range | IO_L15P_T2_DQS_RDWR_B_14     | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V1         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| V2         |             | High Range | IO_L5P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V3         |             | High Range | IO_L6P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V4         |             | High Range | IO_L11N_T1_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V5         |             | High Range | IO_L16N_T2_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V6         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| V7         |             | High Range | IO_L19N_T3_VREF_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V8         |             | High Range | IO_L14N_T2_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V9         |             | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| V10        |             | Dedicated  | PROGRAM_B_0                  | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V11        |             | Dedicated  | CFGBVS_0                     | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V12        |             | Dedicated  | M0_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V13        |             | High Range | IO_L24P_T3_A01_D17_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V14        |             | High Range | IO_L24N_T3_A00_D16_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V15        | sw[5]       | High Range | IO_L21P_T3_DQS_14            | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| V16        | sw[1]       | High Range | IO_L19P_T3_A10_D26_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| V17        | sw[0]       | High Range | IO_L19N_T3_A09_D25_VREF_14   | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| V18        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| V19        |             | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| W2         |             | High Range | IO_L5N_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W3         |             | High Range | IO_L6N_T0_VREF_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W4         |             | High Range | IO_L12N_T1_MRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W5         | clk         | High Range | IO_L12P_T1_MRCC_34           | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W6         |             | High Range | IO_L13N_T2_MRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W7         |             | High Range | IO_L13P_T2_MRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W8         |             | Dedicated  | TDO_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W9         |             | Dedicated  | TMS_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W10        |             | Dedicated  | TDI_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W11        |             | Dedicated  | M1_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| W13        | sw[7]       | High Range | IO_L22P_T3_A05_D21_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W14        | sw[6]       | High Range | IO_L22N_T3_A04_D20_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W15        | sw[4]       | High Range | IO_L21N_T3_DQS_A06_D22_14    | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W16        | sw[2]       | High Range | IO_L20P_T3_A08_D24_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W17        | sw[3]       | High Range | IO_L20N_T3_A07_D23_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W18        |             | High Range | IO_L16P_T2_CSI_B_14          | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W19        | btnL        | High Range | IO_L16N_T2_A15_D31_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_methodology_drc_routed.pb b/tp5_n/tp5_n.runs/impl_1/digi_code_methodology_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..44d27eca0b4f9e2632f902f3d5aa2ab5ea65e816
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/digi_code_methodology_drc_routed.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_methodology_drc_routed.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_methodology_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..da27ce7ff4d01187d75f99788950caed48c24b1e
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_methodology_drc_routed.rpt
@@ -0,0 +1,110 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 11:04:20 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_methodology -file digi_code_methodology_drc_routed.rpt -pb digi_code_methodology_drc_routed.pb -rpx digi_code_methodology_drc_routed.rpx
+| Design       : digi_code
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Fully Routed
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+             Max checks: <unlimited>
+             Checks found: 15
++-----------+----------+-------------------------------+--------+
+| Rule      | Severity | Description                   | Checks |
++-----------+----------+-------------------------------+--------+
+| TIMING-18 | Warning  | Missing input or output delay | 15     |
++-----------+----------+-------------------------------+--------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-18#1 Warning
+Missing input or output delay  
+An input delay is missing on btnC relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#2 Warning
+Missing input or output delay  
+An input delay is missing on btnD relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#3 Warning
+Missing input or output delay  
+An input delay is missing on btnL relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#4 Warning
+Missing input or output delay  
+An input delay is missing on btnR relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#5 Warning
+Missing input or output delay  
+An input delay is missing on btnU relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#6 Warning
+Missing input or output delay  
+An input delay is missing on sw[0] relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#7 Warning
+Missing input or output delay  
+An input delay is missing on sw[1] relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#8 Warning
+Missing input or output delay  
+An input delay is missing on sw[2] relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#9 Warning
+Missing input or output delay  
+An input delay is missing on sw[3] relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#10 Warning
+Missing input or output delay  
+An input delay is missing on sw[4] relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#11 Warning
+Missing input or output delay  
+An input delay is missing on sw[5] relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#12 Warning
+Missing input or output delay  
+An input delay is missing on sw[6] relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#13 Warning
+Missing input or output delay  
+An input delay is missing on sw[7] relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#14 Warning
+Missing input or output delay  
+An output delay is missing on led[0] relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+TIMING-18#15 Warning
+Missing input or output delay  
+An output delay is missing on led[1] relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_opt.dcp b/tp5_n/tp5_n.runs/impl_1/digi_code_opt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..c38609efe8ae76984205dfb9b6b7e265d2e9db75
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diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_physopt.dcp b/tp5_n/tp5_n.runs/impl_1/digi_code_physopt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..661467a85122f17baf1815f324f68e32947eea63
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/digi_code_physopt.dcp differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_placed.dcp b/tp5_n/tp5_n.runs/impl_1/digi_code_placed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..df026a592ca160081b268f35e51e101619a068ef
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/digi_code_placed.dcp differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_power_routed.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_power_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..3b8e357c49bcbdcf7a40112e88d211f8bec2272d
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_power_routed.rpt
@@ -0,0 +1,146 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version     : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date             : Tue Apr 29 11:04:21 2025
+| Host             : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command          : report_power -file digi_code_power_routed.rpt -pb digi_code_power_summary_routed.pb -rpx digi_code_power_routed.rpx
+| Design           : digi_code
+| Device           : xc7a35tcpg236-1
+| Design State     : routed
+| Grade            : commercial
+| Process          : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W)  | 0.073        |
+| Design Power Budget (W)  | Unspecified* |
+| Power Budget Margin (W)  | NA           |
+| Dynamic (W)              | 0.002        |
+| Device Static (W)        | 0.072        |
+| Effective TJA (C/W)      | 5.0          |
+| Max Ambient (C)          | 84.6         |
+| Junction Temperature (C) | 25.4         |
+| Confidence Level         | Low          |
+| Setting File             | ---          |
+| Simulation Activity File | ---          |
+| Design Nets Matched      | NA           |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Clocks         |    <0.001 |        3 |       --- |             --- |
+| Slice Logic    |    <0.001 |       97 |       --- |             --- |
+|   LUT as Logic |    <0.001 |       19 |     20800 |            0.09 |
+|   CARRY4       |    <0.001 |       10 |      8150 |            0.12 |
+|   Register     |    <0.001 |       53 |     41600 |            0.13 |
+|   Others       |     0.000 |       14 |       --- |             --- |
+| Signals        |    <0.001 |       85 |       --- |             --- |
+| I/O            |    <0.001 |       16 |       106 |           15.09 |
+| Static Power   |     0.072 |          |           |                 |
+| Total          |     0.073 |          |           |                 |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint    |       1.000 |     0.010 |       0.001 |      0.010 |       NA    | Unspecified | NA         |
+| Vccaux    |       1.800 |     0.013 |       0.000 |      0.013 |       NA    | Unspecified | NA         |
+| Vcco33    |       3.300 |     0.001 |       0.000 |      0.001 |       NA    | Unspecified | NA         |
+| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High       | Design is routed                                       |                                                                                                            |
+| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
+| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
+| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models               | High       | Device models are Production                           |                                                                                                            |
+|                             |            |                                                        |                                                                                                            |
+| Overall confidence level    | Low        |                                                        |                                                                                                            |
++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C)      | 25.0                     |
+| ThetaJA (C/W)         | 5.0                      |
+| Airflow (LFM)         | 250                      |
+| Heat Sink             | medium (Medium Profile)  |
+| ThetaSA (C/W)         | 4.6                      |
+| Board Selection       | medium (10"x10")         |
+| # of Board Layers     | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0                     |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++-------------+--------+-----------------+
+| Clock       | Domain | Constraint (ns) |
++-------------+--------+-----------------+
+| sys_clk_pin | clk    |            10.0 |
++-------------+--------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++-----------+-----------+
+| Name      | Power (W) |
++-----------+-----------+
+| digi_code |     0.002 |
++-----------+-----------+
+
+
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_power_summary_routed.pb b/tp5_n/tp5_n.runs/impl_1/digi_code_power_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..9716e8d767422a3545b2a9369f782da977eb26c5
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/digi_code_power_summary_routed.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_route_status.pb b/tp5_n/tp5_n.runs/impl_1/digi_code_route_status.pb
new file mode 100644
index 0000000000000000000000000000000000000000..8107ad4e6b4431d7d9ddcdc16fcebcf4ca65945b
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/digi_code_route_status.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_route_status.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_route_status.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..375cc03ef651058d83eadc78f447b3357fa3c144
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_route_status.rpt
@@ -0,0 +1,11 @@
+Design Route Status
+                                               :      # nets :
+   ------------------------------------------- : ----------- :
+   # of logical nets.......................... :         134 :
+       # of nets not needing routing.......... :          45 :
+           # of internally routed nets........ :          45 :
+       # of routable nets..................... :          89 :
+           # of fully routed nets............. :          89 :
+       # of nets with routing errors.......... :           0 :
+   ------------------------------------------- : ----------- :
+
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_routed.dcp b/tp5_n/tp5_n.runs/impl_1/digi_code_routed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..fed149054bc83add646fa285d971bdbc980e8a0b
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/digi_code_routed.dcp differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_timing_summary_routed.pb b/tp5_n/tp5_n.runs/impl_1/digi_code_timing_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..b0511fb41948f6c175d062acedbdd8a77623f248
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/digi_code_timing_summary_routed.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_timing_summary_routed.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_timing_summary_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..0c858b322b681133aa23c5e127dc93ff01c3baaa
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_timing_summary_routed.rpt
@@ -0,0 +1,2220 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 11:04:20 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_timing_summary -max_paths 10 -report_unconstrained -file digi_code_timing_summary_routed.rpt -pb digi_code_timing_summary_routed.pb -rpx digi_code_timing_summary_routed.rpx -warn_on_violation
+| Design       : digi_code
+| Device       : 7a35t-cpg236
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+  Enable Multi Corner Analysis               :  Yes
+  Enable Pessimism Removal                   :  Yes
+  Pessimism Removal Resolution               :  Nearest Common Node
+  Enable Input Delay Default Clock           :  No
+  Enable Preset / Clear Arcs                 :  No
+  Disable Flight Delays                      :  No
+  Ignore I/O Paths                           :  No
+  Timing Early Launch at Borrowing Latches   :  No
+  Borrow Time for Max Delay Exceptions       :  Yes
+  Merge Timing Exceptions                    :  Yes
+  Inter-SLR Compensation                     :  Conservative
+
+  Corner  Analyze    Analyze    
+  Name    Max Paths  Min Paths  
+  ------  ---------  ---------  
+  Slow    Yes        Yes        
+  Fast    Yes        Yes        
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule       Severity  Description                    Violations  
+---------  --------  -----------------------------  ----------  
+TIMING-18  Warning   Missing input or output delay  15          
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (0)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (0)
+5. checking no_input_delay (13)
+6. checking no_output_delay (2)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (0)
+------------------------
+ There are 0 register/latch pins with no clock.
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (0)
+------------------------------------------------
+ There are 0 pins that are not constrained for maximum delay.
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (13)
+-------------------------------
+ There are 13 input ports with no input delay specified. (HIGH)
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (2)
+-------------------------------
+ There are 2 ports with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+      6.381        0.000                      0                   63        0.121        0.000                      0                   63        4.500        0.000                       0                    54  
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock        Waveform(ns)       Period(ns)      Frequency(MHz)
+-----        ------------       ----------      --------------
+sys_clk_pin  {0.000 5.000}      10.000          100.000         
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+sys_clk_pin         6.381        0.000                      0                   63        0.121        0.000                      0                   63        4.500        0.000                       0                    54  
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+
+
+------------------------------------------------------------------------------------------------
+| User Ignored Path Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock    
+----------    ----------    --------    
+
+
+------------------------------------------------------------------------------------------------
+| Unconstrained Path Table
+| ------------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock    
+----------    ----------    --------    
+(none)        sys_clk_pin                 
+(none)                      sys_clk_pin   
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  sys_clk_pin
+  To Clock:  sys_clk_pin
+
+Setup :            0  Failing Endpoints,  Worst Slack        6.381ns,  Total Violation        0.000ns
+Hold  :            0  Failing Endpoints,  Worst Slack        0.121ns,  Total Violation        0.000ns
+PW    :            0  Failing Endpoints,  Worst Slack        4.500ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             6.381ns  (required time - arrival time)
+  Source:                 clk_divide/q_reg[5]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clk_divide/E190_reg/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        3.637ns  (logic 1.977ns (54.359%)  route 1.660ns (45.641%))
+  Logic Levels:           5  (CARRY4=4 LUT2=1)
+  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns = ( 14.855 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.157ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.636     5.157    clk_divide/CLK
+    SLICE_X1Y10          FDRE                                         r  clk_divide/q_reg[5]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y10          FDRE (Prop_fdre_C_Q)         0.456     5.613 r  clk_divide/q_reg[5]/Q
+                         net (fo=2, routed)           0.832     6.445    clk_divide/q_reg[5]
+    SLICE_X0Y10          CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.656     7.101 r  clk_divide/E190_reg_i_5/CO[3]
+                         net (fo=1, routed)           0.000     7.101    clk_divide/E190_reg_i_5_n_0
+    SLICE_X0Y11          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.215 r  clk_divide/E190_reg_i_4/CO[3]
+                         net (fo=1, routed)           0.000     7.215    clk_divide/E190_reg_i_4_n_0
+    SLICE_X0Y12          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.329 r  clk_divide/E190_reg_i_3/CO[3]
+                         net (fo=1, routed)           0.000     7.329    clk_divide/E190_reg_i_3_n_0
+    SLICE_X0Y13          CARRY4 (Prop_carry4_CI_O[1])
+                                                      0.334     7.663 r  clk_divide/E190_reg_i_2/O[1]
+                         net (fo=1, routed)           0.828     8.491    clk_divide/plusOp[18]
+    SLICE_X2Y14          LUT2 (Prop_lut2_I0_O)        0.303     8.794 r  clk_divide/E190_i_1/O
+                         net (fo=1, routed)           0.000     8.794    clk_divide/E190_i_1_n_0
+    SLICE_X2Y14          FDRE                                         r  clk_divide/E190_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514    14.855    clk_divide/CLK
+    SLICE_X2Y14          FDRE                                         r  clk_divide/E190_reg/C
+                         clock pessimism              0.274    15.129    
+                         clock uncertainty           -0.035    15.094    
+    SLICE_X2Y14          FDRE (Setup_fdre_C_D)        0.081    15.175    clk_divide/E190_reg
+  -------------------------------------------------------------------
+                         required time                         15.175    
+                         arrival time                          -8.794    
+  -------------------------------------------------------------------
+                         slack                                  6.381    
+
+Slack (MET) :             6.662ns  (required time - arrival time)
+  Source:                 btn3_pulse/q_signals_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            FSM_sequential_state_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        3.307ns  (logic 0.964ns (29.149%)  route 2.343ns (70.851%))
+  Logic Levels:           3  (LUT6=3)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns = ( 14.855 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.154ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.633     5.154    btn3_pulse/CLK
+    SLICE_X3Y13          FDRE                                         r  btn3_pulse/q_signals_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y13          FDRE (Prop_fdre_C_Q)         0.419     5.573 r  btn3_pulse/q_signals_reg[4]/Q
+                         net (fo=2, routed)           0.829     6.402    btn3_pulse/p_4_in
+    SLICE_X2Y13          LUT6 (Prop_lut6_I0_O)        0.297     6.699 r  btn3_pulse/FSM_sequential_state[2]_i_3/O
+                         net (fo=4, routed)           0.813     7.512    btn3_pulse/FSM_sequential_state[2]_i_3_n_0
+    SLICE_X0Y14          LUT6 (Prop_lut6_I1_O)        0.124     7.636 r  btn3_pulse/FSM_sequential_state[0]_i_2/O
+                         net (fo=1, routed)           0.701     8.337    btn3_pulse/FSM_sequential_state[0]_i_2_n_0
+    SLICE_X1Y14          LUT6 (Prop_lut6_I2_O)        0.124     8.461 r  btn3_pulse/FSM_sequential_state[0]_i_1/O
+                         net (fo=1, routed)           0.000     8.461    btn3_pulse_n_0
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514    14.855    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[0]/C
+                         clock pessimism              0.274    15.129    
+                         clock uncertainty           -0.035    15.094    
+    SLICE_X1Y14          FDRE (Setup_fdre_C_D)        0.029    15.123    FSM_sequential_state_reg[0]
+  -------------------------------------------------------------------
+                         required time                         15.123    
+                         arrival time                          -8.461    
+  -------------------------------------------------------------------
+                         slack                                  6.662    
+
+Slack (MET) :             6.969ns  (required time - arrival time)
+  Source:                 btn2_pulse/q_signals_reg[3]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            FSM_sequential_state_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        3.002ns  (logic 0.828ns (27.581%)  route 2.174ns (72.419%))
+  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns = ( 14.855 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.154ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.633     5.154    btn2_pulse/CLK
+    SLICE_X3Y13          FDRE                                         r  btn2_pulse/q_signals_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y13          FDRE (Prop_fdre_C_Q)         0.456     5.610 r  btn2_pulse/q_signals_reg[3]/Q
+                         net (fo=2, routed)           0.872     6.482    btn2_pulse/p_3_in
+    SLICE_X3Y13          LUT3 (Prop_lut3_I0_O)        0.124     6.606 r  btn2_pulse/FSM_sequential_state[2]_i_5/O
+                         net (fo=4, routed)           0.890     7.496    btn3_pulse/output
+    SLICE_X2Y13          LUT6 (Prop_lut6_I4_O)        0.124     7.620 r  btn3_pulse/FSM_sequential_state[1]_i_2/O
+                         net (fo=1, routed)           0.412     8.032    btn3_pulse/FSM_sequential_state[1]_i_2_n_0
+    SLICE_X1Y14          LUT5 (Prop_lut5_I2_O)        0.124     8.156 r  btn3_pulse/FSM_sequential_state[1]_i_1/O
+                         net (fo=1, routed)           0.000     8.156    btn3_pulse_n_1
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514    14.855    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[1]/C
+                         clock pessimism              0.274    15.129    
+                         clock uncertainty           -0.035    15.094    
+    SLICE_X1Y14          FDRE (Setup_fdre_C_D)        0.031    15.125    FSM_sequential_state_reg[1]
+  -------------------------------------------------------------------
+                         required time                         15.125    
+                         arrival time                          -8.156    
+  -------------------------------------------------------------------
+                         slack                                  6.969    
+
+Slack (MET) :             7.072ns  (required time - arrival time)
+  Source:                 btn3_pulse/q_signals_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            FSM_sequential_state_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.898ns  (logic 0.964ns (33.262%)  route 1.934ns (66.738%))
+  Logic Levels:           3  (LUT6=3)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns = ( 14.855 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.154ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.633     5.154    btn3_pulse/CLK
+    SLICE_X3Y13          FDRE                                         r  btn3_pulse/q_signals_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y13          FDRE (Prop_fdre_C_Q)         0.419     5.573 r  btn3_pulse/q_signals_reg[4]/Q
+                         net (fo=2, routed)           0.829     6.402    btn3_pulse/p_4_in
+    SLICE_X2Y13          LUT6 (Prop_lut6_I0_O)        0.297     6.699 r  btn3_pulse/FSM_sequential_state[2]_i_3/O
+                         net (fo=4, routed)           0.814     7.513    btn3_pulse/FSM_sequential_state[2]_i_3_n_0
+    SLICE_X0Y14          LUT6 (Prop_lut6_I2_O)        0.124     7.637 r  btn3_pulse/FSM_sequential_state[2]_i_2/O
+                         net (fo=1, routed)           0.291     7.928    btnReset_pulse/FSM_sequential_state_reg[2]
+    SLICE_X1Y14          LUT6 (Prop_lut6_I1_O)        0.124     8.052 r  btnReset_pulse/FSM_sequential_state[2]_i_1/O
+                         net (fo=1, routed)           0.000     8.052    btnReset_pulse_n_1
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514    14.855    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[2]/C
+                         clock pessimism              0.274    15.129    
+                         clock uncertainty           -0.035    15.094    
+    SLICE_X1Y14          FDRE (Setup_fdre_C_D)        0.031    15.125    FSM_sequential_state_reg[2]
+  -------------------------------------------------------------------
+                         required time                         15.125    
+                         arrival time                          -8.052    
+  -------------------------------------------------------------------
+                         slack                                  7.072    
+
+Slack (MET) :             7.562ns  (required time - arrival time)
+  Source:                 clk_divide/q_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clk_divide/q_reg[17]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.437ns  (logic 1.806ns (74.116%)  route 0.631ns (25.884%))
+  Logic Levels:           5  (CARRY4=5)
+  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns = ( 14.855 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.157ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.636     5.157    clk_divide/CLK
+    SLICE_X1Y9           FDRE                                         r  clk_divide/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y9           FDRE (Prop_fdre_C_Q)         0.456     5.613 r  clk_divide/q_reg[1]/Q
+                         net (fo=2, routed)           0.631     6.244    clk_divide/q_reg[1]
+    SLICE_X1Y9           CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     6.918 r  clk_divide/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     6.918    clk_divide/q_reg[0]_i_1_n_0
+    SLICE_X1Y10          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.032 r  clk_divide/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.032    clk_divide/q_reg[4]_i_1_n_0
+    SLICE_X1Y11          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.146 r  clk_divide/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.146    clk_divide/q_reg[8]_i_1_n_0
+    SLICE_X1Y12          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.260 r  clk_divide/q_reg[12]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.260    clk_divide/q_reg[12]_i_1_n_0
+    SLICE_X1Y13          CARRY4 (Prop_carry4_CI_O[1])
+                                                      0.334     7.594 r  clk_divide/q_reg[16]_i_1/O[1]
+                         net (fo=1, routed)           0.000     7.594    clk_divide/q_reg[16]_i_1_n_6
+    SLICE_X1Y13          FDRE                                         r  clk_divide/q_reg[17]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514    14.855    clk_divide/CLK
+    SLICE_X1Y13          FDRE                                         r  clk_divide/q_reg[17]/C
+                         clock pessimism              0.274    15.129    
+                         clock uncertainty           -0.035    15.094    
+    SLICE_X1Y13          FDRE (Setup_fdre_C_D)        0.062    15.156    clk_divide/q_reg[17]
+  -------------------------------------------------------------------
+                         required time                         15.156    
+                         arrival time                          -7.594    
+  -------------------------------------------------------------------
+                         slack                                  7.562    
+
+Slack (MET) :             7.657ns  (required time - arrival time)
+  Source:                 clk_divide/q_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clk_divide/q_reg[18]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.342ns  (logic 1.711ns (73.066%)  route 0.631ns (26.934%))
+  Logic Levels:           5  (CARRY4=5)
+  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns = ( 14.855 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.157ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.636     5.157    clk_divide/CLK
+    SLICE_X1Y9           FDRE                                         r  clk_divide/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y9           FDRE (Prop_fdre_C_Q)         0.456     5.613 r  clk_divide/q_reg[1]/Q
+                         net (fo=2, routed)           0.631     6.244    clk_divide/q_reg[1]
+    SLICE_X1Y9           CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     6.918 r  clk_divide/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     6.918    clk_divide/q_reg[0]_i_1_n_0
+    SLICE_X1Y10          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.032 r  clk_divide/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.032    clk_divide/q_reg[4]_i_1_n_0
+    SLICE_X1Y11          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.146 r  clk_divide/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.146    clk_divide/q_reg[8]_i_1_n_0
+    SLICE_X1Y12          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.260 r  clk_divide/q_reg[12]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.260    clk_divide/q_reg[12]_i_1_n_0
+    SLICE_X1Y13          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.499 r  clk_divide/q_reg[16]_i_1/O[2]
+                         net (fo=1, routed)           0.000     7.499    clk_divide/q_reg[16]_i_1_n_5
+    SLICE_X1Y13          FDRE                                         r  clk_divide/q_reg[18]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514    14.855    clk_divide/CLK
+    SLICE_X1Y13          FDRE                                         r  clk_divide/q_reg[18]/C
+                         clock pessimism              0.274    15.129    
+                         clock uncertainty           -0.035    15.094    
+    SLICE_X1Y13          FDRE (Setup_fdre_C_D)        0.062    15.156    clk_divide/q_reg[18]
+  -------------------------------------------------------------------
+                         required time                         15.156    
+                         arrival time                          -7.499    
+  -------------------------------------------------------------------
+                         slack                                  7.657    
+
+Slack (MET) :             7.673ns  (required time - arrival time)
+  Source:                 clk_divide/q_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clk_divide/q_reg[16]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.326ns  (logic 1.695ns (72.880%)  route 0.631ns (27.120%))
+  Logic Levels:           5  (CARRY4=5)
+  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns = ( 14.855 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.157ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.636     5.157    clk_divide/CLK
+    SLICE_X1Y9           FDRE                                         r  clk_divide/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y9           FDRE (Prop_fdre_C_Q)         0.456     5.613 r  clk_divide/q_reg[1]/Q
+                         net (fo=2, routed)           0.631     6.244    clk_divide/q_reg[1]
+    SLICE_X1Y9           CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     6.918 r  clk_divide/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     6.918    clk_divide/q_reg[0]_i_1_n_0
+    SLICE_X1Y10          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.032 r  clk_divide/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.032    clk_divide/q_reg[4]_i_1_n_0
+    SLICE_X1Y11          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.146 r  clk_divide/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.146    clk_divide/q_reg[8]_i_1_n_0
+    SLICE_X1Y12          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.260 r  clk_divide/q_reg[12]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.260    clk_divide/q_reg[12]_i_1_n_0
+    SLICE_X1Y13          CARRY4 (Prop_carry4_CI_O[0])
+                                                      0.223     7.483 r  clk_divide/q_reg[16]_i_1/O[0]
+                         net (fo=1, routed)           0.000     7.483    clk_divide/q_reg[16]_i_1_n_7
+    SLICE_X1Y13          FDRE                                         r  clk_divide/q_reg[16]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514    14.855    clk_divide/CLK
+    SLICE_X1Y13          FDRE                                         r  clk_divide/q_reg[16]/C
+                         clock pessimism              0.274    15.129    
+                         clock uncertainty           -0.035    15.094    
+    SLICE_X1Y13          FDRE (Setup_fdre_C_D)        0.062    15.156    clk_divide/q_reg[16]
+  -------------------------------------------------------------------
+                         required time                         15.156    
+                         arrival time                          -7.483    
+  -------------------------------------------------------------------
+                         slack                                  7.673    
+
+Slack (MET) :             7.677ns  (required time - arrival time)
+  Source:                 clk_divide/q_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clk_divide/q_reg[13]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.323ns  (logic 1.692ns (72.845%)  route 0.631ns (27.155%))
+  Logic Levels:           4  (CARRY4=4)
+  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.856ns = ( 14.856 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.157ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.636     5.157    clk_divide/CLK
+    SLICE_X1Y9           FDRE                                         r  clk_divide/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y9           FDRE (Prop_fdre_C_Q)         0.456     5.613 r  clk_divide/q_reg[1]/Q
+                         net (fo=2, routed)           0.631     6.244    clk_divide/q_reg[1]
+    SLICE_X1Y9           CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     6.918 r  clk_divide/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     6.918    clk_divide/q_reg[0]_i_1_n_0
+    SLICE_X1Y10          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.032 r  clk_divide/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.032    clk_divide/q_reg[4]_i_1_n_0
+    SLICE_X1Y11          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.146 r  clk_divide/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.146    clk_divide/q_reg[8]_i_1_n_0
+    SLICE_X1Y12          CARRY4 (Prop_carry4_CI_O[1])
+                                                      0.334     7.480 r  clk_divide/q_reg[12]_i_1/O[1]
+                         net (fo=1, routed)           0.000     7.480    clk_divide/q_reg[12]_i_1_n_6
+    SLICE_X1Y12          FDRE                                         r  clk_divide/q_reg[13]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.515    14.856    clk_divide/CLK
+    SLICE_X1Y12          FDRE                                         r  clk_divide/q_reg[13]/C
+                         clock pessimism              0.274    15.130    
+                         clock uncertainty           -0.035    15.095    
+    SLICE_X1Y12          FDRE (Setup_fdre_C_D)        0.062    15.157    clk_divide/q_reg[13]
+  -------------------------------------------------------------------
+                         required time                         15.157    
+                         arrival time                          -7.480    
+  -------------------------------------------------------------------
+                         slack                                  7.677    
+
+Slack (MET) :             7.698ns  (required time - arrival time)
+  Source:                 clk_divide/q_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clk_divide/q_reg[15]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.302ns  (logic 1.671ns (72.598%)  route 0.631ns (27.402%))
+  Logic Levels:           4  (CARRY4=4)
+  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.856ns = ( 14.856 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.157ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.636     5.157    clk_divide/CLK
+    SLICE_X1Y9           FDRE                                         r  clk_divide/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y9           FDRE (Prop_fdre_C_Q)         0.456     5.613 r  clk_divide/q_reg[1]/Q
+                         net (fo=2, routed)           0.631     6.244    clk_divide/q_reg[1]
+    SLICE_X1Y9           CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     6.918 r  clk_divide/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     6.918    clk_divide/q_reg[0]_i_1_n_0
+    SLICE_X1Y10          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.032 r  clk_divide/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.032    clk_divide/q_reg[4]_i_1_n_0
+    SLICE_X1Y11          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.146 r  clk_divide/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.146    clk_divide/q_reg[8]_i_1_n_0
+    SLICE_X1Y12          CARRY4 (Prop_carry4_CI_O[3])
+                                                      0.313     7.459 r  clk_divide/q_reg[12]_i_1/O[3]
+                         net (fo=1, routed)           0.000     7.459    clk_divide/q_reg[12]_i_1_n_4
+    SLICE_X1Y12          FDRE                                         r  clk_divide/q_reg[15]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.515    14.856    clk_divide/CLK
+    SLICE_X1Y12          FDRE                                         r  clk_divide/q_reg[15]/C
+                         clock pessimism              0.274    15.130    
+                         clock uncertainty           -0.035    15.095    
+    SLICE_X1Y12          FDRE (Setup_fdre_C_D)        0.062    15.157    clk_divide/q_reg[15]
+  -------------------------------------------------------------------
+                         required time                         15.157    
+                         arrival time                          -7.459    
+  -------------------------------------------------------------------
+                         slack                                  7.698    
+
+Slack (MET) :             7.772ns  (required time - arrival time)
+  Source:                 clk_divide/q_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clk_divide/q_reg[14]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.228ns  (logic 1.597ns (71.687%)  route 0.631ns (28.313%))
+  Logic Levels:           4  (CARRY4=4)
+  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.856ns = ( 14.856 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.157ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.636     5.157    clk_divide/CLK
+    SLICE_X1Y9           FDRE                                         r  clk_divide/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y9           FDRE (Prop_fdre_C_Q)         0.456     5.613 r  clk_divide/q_reg[1]/Q
+                         net (fo=2, routed)           0.631     6.244    clk_divide/q_reg[1]
+    SLICE_X1Y9           CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     6.918 r  clk_divide/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     6.918    clk_divide/q_reg[0]_i_1_n_0
+    SLICE_X1Y10          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.032 r  clk_divide/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.032    clk_divide/q_reg[4]_i_1_n_0
+    SLICE_X1Y11          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.146 r  clk_divide/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.146    clk_divide/q_reg[8]_i_1_n_0
+    SLICE_X1Y12          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.385 r  clk_divide/q_reg[12]_i_1/O[2]
+                         net (fo=1, routed)           0.000     7.385    clk_divide/q_reg[12]_i_1_n_5
+    SLICE_X1Y12          FDRE                                         r  clk_divide/q_reg[14]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.515    14.856    clk_divide/CLK
+    SLICE_X1Y12          FDRE                                         r  clk_divide/q_reg[14]/C
+                         clock pessimism              0.274    15.130    
+                         clock uncertainty           -0.035    15.095    
+    SLICE_X1Y12          FDRE (Setup_fdre_C_D)        0.062    15.157    clk_divide/q_reg[14]
+  -------------------------------------------------------------------
+                         required time                         15.157    
+                         arrival time                          -7.385    
+  -------------------------------------------------------------------
+                         slack                                  7.772    
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             0.121ns  (arrival time - required time)
+  Source:                 btn1_pulse/q_signals_reg[0]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btn1_pulse/q_signals_reg[3]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.254ns  (logic 0.186ns (73.141%)  route 0.068ns (26.859%))
+  Logic Levels:           1  (LUT3=1)
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    1.474ns
+    Clock Pessimism Removal (CPR):    0.501ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    btn1_pulse/CLK
+    SLICE_X3Y14          FDRE                                         r  btn1_pulse/q_signals_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y14          FDRE (Prop_fdre_C_Q)         0.141     1.615 r  btn1_pulse/q_signals_reg[0]/Q
+                         net (fo=2, routed)           0.068     1.683    btn1_pulse/q_signals_reg_n_0_[0]
+    SLICE_X2Y14          LUT3 (Prop_lut3_I0_O)        0.045     1.728 r  btn1_pulse/p_5_out/O
+                         net (fo=1, routed)           0.000     1.728    btn1_pulse/p_5_out__0[3]
+    SLICE_X2Y14          FDRE                                         r  btn1_pulse/q_signals_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn1_pulse/CLK
+    SLICE_X2Y14          FDRE                                         r  btn1_pulse/q_signals_reg[3]/C
+                         clock pessimism             -0.501     1.487    
+    SLICE_X2Y14          FDRE (Hold_fdre_C_D)         0.120     1.607    btn1_pulse/q_signals_reg[3]
+  -------------------------------------------------------------------
+                         required time                         -1.607    
+                         arrival time                           1.728    
+  -------------------------------------------------------------------
+                         slack                                  0.121    
+
+Slack (MET) :             0.132ns  (arrival time - required time)
+  Source:                 btn3_pulse/q_signals_reg[3]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btn3_pulse/q_signals_reg[4]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.208ns  (logic 0.141ns (67.788%)  route 0.067ns (32.212%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    1.474ns
+    Clock Pessimism Removal (CPR):    0.514ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    btn3_pulse/CLK
+    SLICE_X3Y13          FDRE                                         r  btn3_pulse/q_signals_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y13          FDRE (Prop_fdre_C_Q)         0.141     1.615 r  btn3_pulse/q_signals_reg[3]/Q
+                         net (fo=2, routed)           0.067     1.682    btn3_pulse/p_3_in
+    SLICE_X3Y13          FDRE                                         r  btn3_pulse/q_signals_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn3_pulse/CLK
+    SLICE_X3Y13          FDRE                                         r  btn3_pulse/q_signals_reg[4]/C
+                         clock pessimism             -0.514     1.474    
+    SLICE_X3Y13          FDRE (Hold_fdre_C_D)         0.076     1.550    btn3_pulse/q_signals_reg[4]
+  -------------------------------------------------------------------
+                         required time                         -1.550    
+                         arrival time                           1.682    
+  -------------------------------------------------------------------
+                         slack                                  0.132    
+
+Slack (MET) :             0.154ns  (arrival time - required time)
+  Source:                 btnReset_pulse/q_signals_reg[3]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btnReset_pulse/q_signals_reg[4]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.229ns  (logic 0.141ns (61.696%)  route 0.088ns (38.304%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    1.474ns
+    Clock Pessimism Removal (CPR):    0.514ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    btnReset_pulse/CLK
+    SLICE_X0Y14          FDRE                                         r  btnReset_pulse/q_signals_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y14          FDRE (Prop_fdre_C_Q)         0.141     1.615 r  btnReset_pulse/q_signals_reg[3]/Q
+                         net (fo=3, routed)           0.088     1.703    btnReset_pulse/p_3_in
+    SLICE_X0Y14          FDRE                                         r  btnReset_pulse/q_signals_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btnReset_pulse/CLK
+    SLICE_X0Y14          FDRE                                         r  btnReset_pulse/q_signals_reg[4]/C
+                         clock pessimism             -0.514     1.474    
+    SLICE_X0Y14          FDRE (Hold_fdre_C_D)         0.075     1.549    btnReset_pulse/q_signals_reg[4]
+  -------------------------------------------------------------------
+                         required time                         -1.549    
+                         arrival time                           1.703    
+  -------------------------------------------------------------------
+                         slack                                  0.154    
+
+Slack (MET) :             0.154ns  (arrival time - required time)
+  Source:                 btn2_pulse/q_signals_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btn2_pulse/q_signals_reg[3]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.259ns  (logic 0.209ns (80.663%)  route 0.050ns (19.337%))
+  Logic Levels:           1  (LUT3=1)
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    1.474ns
+    Clock Pessimism Removal (CPR):    0.501ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    btn2_pulse/CLK
+    SLICE_X2Y13          FDRE                                         r  btn2_pulse/q_signals_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X2Y13          FDRE (Prop_fdre_C_Q)         0.164     1.638 r  btn2_pulse/q_signals_reg[2]/Q
+                         net (fo=1, routed)           0.050     1.688    btn2_pulse/q_signals_reg_n_0_[2]
+    SLICE_X3Y13          LUT3 (Prop_lut3_I2_O)        0.045     1.733 r  btn2_pulse/p_5_out/O
+                         net (fo=1, routed)           0.000     1.733    btn2_pulse/p_5_out__0[3]
+    SLICE_X3Y13          FDRE                                         r  btn2_pulse/q_signals_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn2_pulse/CLK
+    SLICE_X3Y13          FDRE                                         r  btn2_pulse/q_signals_reg[3]/C
+                         clock pessimism             -0.501     1.487    
+    SLICE_X3Y13          FDRE (Hold_fdre_C_D)         0.092     1.579    btn2_pulse/q_signals_reg[3]
+  -------------------------------------------------------------------
+                         required time                         -1.579    
+                         arrival time                           1.733    
+  -------------------------------------------------------------------
+                         slack                                  0.154    
+
+Slack (MET) :             0.160ns  (arrival time - required time)
+  Source:                 btn1_pulse/q_signals_reg[3]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btn1_pulse/q_signals_reg[4]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.220ns  (logic 0.164ns (74.580%)  route 0.056ns (25.420%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    1.474ns
+    Clock Pessimism Removal (CPR):    0.514ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    btn1_pulse/CLK
+    SLICE_X2Y14          FDRE                                         r  btn1_pulse/q_signals_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X2Y14          FDRE (Prop_fdre_C_Q)         0.164     1.638 r  btn1_pulse/q_signals_reg[3]/Q
+                         net (fo=2, routed)           0.056     1.694    btn1_pulse/p_3_in
+    SLICE_X2Y14          FDRE                                         r  btn1_pulse/q_signals_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn1_pulse/CLK
+    SLICE_X2Y14          FDRE                                         r  btn1_pulse/q_signals_reg[4]/C
+                         clock pessimism             -0.514     1.474    
+    SLICE_X2Y14          FDRE (Hold_fdre_C_D)         0.060     1.534    btn1_pulse/q_signals_reg[4]
+  -------------------------------------------------------------------
+                         required time                         -1.534    
+                         arrival time                           1.694    
+  -------------------------------------------------------------------
+                         slack                                  0.160    
+
+Slack (MET) :             0.187ns  (arrival time - required time)
+  Source:                 btn0_pulse/q_signals_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btn0_pulse/q_signals_reg[3]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.291ns  (logic 0.209ns (71.796%)  route 0.082ns (28.204%))
+  Logic Levels:           1  (LUT3=1)
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    1.474ns
+    Clock Pessimism Removal (CPR):    0.501ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    btn0_pulse/CLK
+    SLICE_X2Y13          FDRE                                         r  btn0_pulse/q_signals_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X2Y13          FDRE (Prop_fdre_C_Q)         0.164     1.638 r  btn0_pulse/q_signals_reg[2]/Q
+                         net (fo=1, routed)           0.082     1.720    btn0_pulse/q_signals_reg_n_0_[2]
+    SLICE_X3Y13          LUT3 (Prop_lut3_I2_O)        0.045     1.765 r  btn0_pulse/p_5_out/O
+                         net (fo=1, routed)           0.000     1.765    btn0_pulse/p_5_out__0[3]
+    SLICE_X3Y13          FDRE                                         r  btn0_pulse/q_signals_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn0_pulse/CLK
+    SLICE_X3Y13          FDRE                                         r  btn0_pulse/q_signals_reg[3]/C
+                         clock pessimism             -0.501     1.487    
+    SLICE_X3Y13          FDRE (Hold_fdre_C_D)         0.091     1.578    btn0_pulse/q_signals_reg[3]
+  -------------------------------------------------------------------
+                         required time                         -1.578    
+                         arrival time                           1.765    
+  -------------------------------------------------------------------
+                         slack                                  0.187    
+
+Slack (MET) :             0.189ns  (arrival time - required time)
+  Source:                 btn2_pulse/q_signals_reg[0]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btn2_pulse/q_signals_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.256ns  (logic 0.141ns (55.160%)  route 0.115ns (44.840%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    1.474ns
+    Clock Pessimism Removal (CPR):    0.499ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    btn2_pulse/CLK
+    SLICE_X0Y13          FDRE                                         r  btn2_pulse/q_signals_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y13          FDRE (Prop_fdre_C_Q)         0.141     1.615 r  btn2_pulse/q_signals_reg[0]/Q
+                         net (fo=2, routed)           0.115     1.730    btn2_pulse/q_signals_reg_n_0_[0]
+    SLICE_X2Y13          FDRE                                         r  btn2_pulse/q_signals_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn2_pulse/CLK
+    SLICE_X2Y13          FDRE                                         r  btn2_pulse/q_signals_reg[1]/C
+                         clock pessimism             -0.499     1.489    
+    SLICE_X2Y13          FDRE (Hold_fdre_C_D)         0.052     1.541    btn2_pulse/q_signals_reg[1]
+  -------------------------------------------------------------------
+                         required time                         -1.541    
+                         arrival time                           1.730    
+  -------------------------------------------------------------------
+                         slack                                  0.189    
+
+Slack (MET) :             0.195ns  (arrival time - required time)
+  Source:                 btnReset_pulse/q_signals_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btnReset_pulse/q_signals_reg[3]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.301ns  (logic 0.186ns (61.716%)  route 0.115ns (38.284%))
+  Logic Levels:           1  (LUT3=1)
+  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    1.474ns
+    Clock Pessimism Removal (CPR):    0.499ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    btnReset_pulse/CLK
+    SLICE_X0Y13          FDRE                                         r  btnReset_pulse/q_signals_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y13          FDRE (Prop_fdre_C_Q)         0.141     1.615 r  btnReset_pulse/q_signals_reg[2]/Q
+                         net (fo=1, routed)           0.115     1.731    btnReset_pulse/q_signals_reg_n_0_[2]
+    SLICE_X0Y14          LUT3 (Prop_lut3_I2_O)        0.045     1.776 r  btnReset_pulse/p_5_out/O
+                         net (fo=1, routed)           0.000     1.776    btnReset_pulse/p_5_out__0[3]
+    SLICE_X0Y14          FDRE                                         r  btnReset_pulse/q_signals_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btnReset_pulse/CLK
+    SLICE_X0Y14          FDRE                                         r  btnReset_pulse/q_signals_reg[3]/C
+                         clock pessimism             -0.499     1.489    
+    SLICE_X0Y14          FDRE (Hold_fdre_C_D)         0.091     1.580    btnReset_pulse/q_signals_reg[3]
+  -------------------------------------------------------------------
+                         required time                         -1.580    
+                         arrival time                           1.776    
+  -------------------------------------------------------------------
+                         slack                                  0.195    
+
+Slack (MET) :             0.198ns  (arrival time - required time)
+  Source:                 btn3_pulse/q_signals_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btn3_pulse/q_signals_reg[3]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.303ns  (logic 0.209ns (68.923%)  route 0.094ns (31.077%))
+  Logic Levels:           1  (LUT3=1)
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    1.474ns
+    Clock Pessimism Removal (CPR):    0.501ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    btn3_pulse/CLK
+    SLICE_X2Y13          FDRE                                         r  btn3_pulse/q_signals_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X2Y13          FDRE (Prop_fdre_C_Q)         0.164     1.638 r  btn3_pulse/q_signals_reg[1]/Q
+                         net (fo=2, routed)           0.094     1.732    btn3_pulse/q_signals_reg_n_0_[1]
+    SLICE_X3Y13          LUT3 (Prop_lut3_I1_O)        0.045     1.777 r  btn3_pulse/p_5_out/O
+                         net (fo=1, routed)           0.000     1.777    btn3_pulse/p_5_out__0[3]
+    SLICE_X3Y13          FDRE                                         r  btn3_pulse/q_signals_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn3_pulse/CLK
+    SLICE_X3Y13          FDRE                                         r  btn3_pulse/q_signals_reg[3]/C
+                         clock pessimism             -0.501     1.487    
+    SLICE_X3Y13          FDRE (Hold_fdre_C_D)         0.092     1.579    btn3_pulse/q_signals_reg[3]
+  -------------------------------------------------------------------
+                         required time                         -1.579    
+                         arrival time                           1.777    
+  -------------------------------------------------------------------
+                         slack                                  0.198    
+
+Slack (MET) :             0.210ns  (arrival time - required time)
+  Source:                 btn0_pulse/q_signals_reg[0]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            btn0_pulse/q_signals_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.257ns  (logic 0.141ns (54.798%)  route 0.116ns (45.202%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    1.474ns
+    Clock Pessimism Removal (CPR):    0.514ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    btn0_pulse/CLK
+    SLICE_X3Y14          FDRE                                         r  btn0_pulse/q_signals_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y14          FDRE (Prop_fdre_C_Q)         0.141     1.615 r  btn0_pulse/q_signals_reg[0]/Q
+                         net (fo=2, routed)           0.116     1.731    btn0_pulse/q_signals_reg_n_0_[0]
+    SLICE_X3Y14          FDRE                                         r  btn0_pulse/q_signals_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn0_pulse/CLK
+    SLICE_X3Y14          FDRE                                         r  btn0_pulse/q_signals_reg[1]/C
+                         clock pessimism             -0.514     1.474    
+    SLICE_X3Y14          FDRE (Hold_fdre_C_D)         0.047     1.521    btn0_pulse/q_signals_reg[1]
+  -------------------------------------------------------------------
+                         required time                         -1.521    
+                         arrival time                           1.731    
+  -------------------------------------------------------------------
+                         slack                                  0.210    
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         sys_clk_pin
+Waveform(ns):       { 0.000 5.000 }
+Period(ns):         10.000
+Sources:            { clk }
+
+Check Type        Corner  Lib Pin  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
+Min Period        n/a     BUFG/I   n/a            2.155         10.000      7.845      BUFGCTRL_X0Y0  clk_IBUF_BUFG_inst/I
+Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X1Y14    FSM_sequential_state_reg[0]/C
+Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X1Y14    FSM_sequential_state_reg[1]/C
+Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X1Y14    FSM_sequential_state_reg[2]/C
+Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X3Y14    btn0_pulse/q_signals_reg[0]/C
+Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X3Y14    btn0_pulse/q_signals_reg[1]/C
+Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X2Y13    btn0_pulse/q_signals_reg[2]/C
+Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X3Y13    btn0_pulse/q_signals_reg[3]/C
+Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X1Y13    btn0_pulse/q_signals_reg[4]/C
+Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X1Y13    btn0_pulse/q_signals_reg[5]/C
+Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[0]/C
+Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[0]/C
+Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[1]/C
+Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[1]/C
+Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[2]/C
+Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[2]/C
+Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X3Y14    btn0_pulse/q_signals_reg[0]/C
+Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X3Y14    btn0_pulse/q_signals_reg[0]/C
+Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X3Y14    btn0_pulse/q_signals_reg[1]/C
+Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X3Y14    btn0_pulse/q_signals_reg[1]/C
+High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[0]/C
+High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[0]/C
+High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[1]/C
+High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[1]/C
+High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[2]/C
+High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X1Y14    FSM_sequential_state_reg[2]/C
+High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X3Y14    btn0_pulse/q_signals_reg[0]/C
+High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X3Y14    btn0_pulse/q_signals_reg[0]/C
+High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X3Y14    btn0_pulse/q_signals_reg[1]/C
+High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X3Y14    btn0_pulse/q_signals_reg[1]/C
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  sys_clk_pin
+  To Clock:  
+
+Max Delay             2 Endpoints
+Min Delay             2 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 FSM_sequential_state_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            led[1]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        7.717ns  (logic 4.110ns (53.253%)  route 3.608ns (46.747%))
+  Logic Levels:           2  (LUT3=1 OBUF=1)
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.633     5.154    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y14          FDRE (Prop_fdre_C_Q)         0.456     5.610 r  FSM_sequential_state_reg[2]/Q
+                         net (fo=5, routed)           1.072     6.682    state[2]
+    SLICE_X0Y14          LUT3 (Prop_lut3_I0_O)        0.124     6.806 r  led_OBUF[1]_inst_i_1/O
+                         net (fo=1, routed)           2.536     9.342    led_OBUF[1]
+    E19                  OBUF (Prop_obuf_I_O)         3.530    12.872 r  led_OBUF[1]_inst/O
+                         net (fo=0)                   0.000    12.872    led[1]
+    E19                                                               r  led[1] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 FSM_sequential_state_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            led[0]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        7.465ns  (logic 4.321ns (57.880%)  route 3.144ns (42.120%))
+  Logic Levels:           2  (LUT3=1 OBUF=1)
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.633     5.154    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y14          FDRE (Prop_fdre_C_Q)         0.456     5.610 f  FSM_sequential_state_reg[2]/Q
+                         net (fo=5, routed)           1.072     6.682    state[2]
+    SLICE_X0Y14          LUT3 (Prop_lut3_I0_O)        0.152     6.834 r  led_OBUF[0]_inst_i_1/O
+                         net (fo=1, routed)           2.072     8.906    led_OBUF[0]
+    U16                  OBUF (Prop_obuf_I_O)         3.713    12.619 r  led_OBUF[0]_inst/O
+                         net (fo=0)                   0.000    12.619    led[0]
+    U16                                                               r  led[0] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 FSM_sequential_state_reg[0]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            led[0]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.095ns  (logic 1.463ns (69.813%)  route 0.633ns (30.187%))
+  Logic Levels:           2  (LUT3=1 OBUF=1)
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y14          FDRE (Prop_fdre_C_Q)         0.141     1.615 r  FSM_sequential_state_reg[0]/Q
+                         net (fo=7, routed)           0.122     1.737    state[0]
+    SLICE_X0Y14          LUT3 (Prop_lut3_I2_O)        0.049     1.786 r  led_OBUF[0]_inst_i_1/O
+                         net (fo=1, routed)           0.510     2.297    led_OBUF[0]
+    U16                  OBUF (Prop_obuf_I_O)         1.273     3.570 r  led_OBUF[0]_inst/O
+                         net (fo=0)                   0.000     3.570    led[0]
+    U16                                                               r  led[0] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 FSM_sequential_state_reg[0]/C
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            led[1]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        2.250ns  (logic 1.417ns (62.972%)  route 0.833ns (37.028%))
+  Logic Levels:           2  (LUT3=1 OBUF=1)
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.591     1.474    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y14          FDRE (Prop_fdre_C_Q)         0.141     1.615 f  FSM_sequential_state_reg[0]/Q
+                         net (fo=7, routed)           0.122     1.737    state[0]
+    SLICE_X0Y14          LUT3 (Prop_lut3_I1_O)        0.045     1.782 r  led_OBUF[1]_inst_i_1/O
+                         net (fo=1, routed)           0.711     2.493    led_OBUF[1]
+    E19                  OBUF (Prop_obuf_I_O)         1.231     3.724 r  led_OBUF[1]_inst/O
+                         net (fo=0)                   0.000     3.724    led[1]
+    E19                                                               r  led[1] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  
+  To Clock:  sys_clk_pin
+
+Max Delay             8 Endpoints
+Min Delay             8 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 sw[0]
+                            (input port)
+  Destination:            FSM_sequential_state_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        3.827ns  (logic 1.701ns (44.448%)  route 2.126ns (55.552%))
+  Logic Levels:           3  (IBUF=1 LUT6=2)
+  Clock Path Skew:        4.855ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    V17                                               0.000     0.000 r  sw[0] (IN)
+                         net (fo=0)                   0.000     0.000    sw[0]
+    V17                  IBUF (Prop_ibuf_I_O)         1.453     1.453 r  sw_IBUF[0]_inst/O
+                         net (fo=1, routed)           1.425     2.877    btn3_pulse/sw_IBUF[0]
+    SLICE_X0Y14          LUT6 (Prop_lut6_I4_O)        0.124     3.001 r  btn3_pulse/FSM_sequential_state[0]_i_2/O
+                         net (fo=1, routed)           0.701     3.703    btn3_pulse/FSM_sequential_state[0]_i_2_n_0
+    SLICE_X1Y14          LUT6 (Prop_lut6_I2_O)        0.124     3.827 r  btn3_pulse/FSM_sequential_state[0]_i_1/O
+                         net (fo=1, routed)           0.000     3.827    btn3_pulse_n_0
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514     4.855    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[0]/C
+
+Slack:                    inf
+  Source:                 sw[4]
+                            (input port)
+  Destination:            FSM_sequential_state_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        3.617ns  (logic 1.699ns (46.971%)  route 1.918ns (53.029%))
+  Logic Levels:           3  (IBUF=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        4.855ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W15                                               0.000     0.000 r  sw[4] (IN)
+                         net (fo=0)                   0.000     0.000    sw[4]
+    W15                  IBUF (Prop_ibuf_I_O)         1.451     1.451 r  sw_IBUF[4]_inst/O
+                         net (fo=1, routed)           1.485     2.936    btn3_pulse/sw_IBUF[4]
+    SLICE_X2Y13          LUT6 (Prop_lut6_I4_O)        0.124     3.060 r  btn3_pulse/FSM_sequential_state[1]_i_3/O
+                         net (fo=2, routed)           0.433     3.493    btn3_pulse/FSM_sequential_state[1]_i_3_n_0
+    SLICE_X1Y14          LUT5 (Prop_lut5_I3_O)        0.124     3.617 r  btn3_pulse/FSM_sequential_state[1]_i_1/O
+                         net (fo=1, routed)           0.000     3.617    btn3_pulse_n_1
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514     4.855    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[1]/C
+
+Slack:                    inf
+  Source:                 sw[6]
+                            (input port)
+  Destination:            FSM_sequential_state_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        3.608ns  (logic 1.698ns (47.059%)  route 1.910ns (52.941%))
+  Logic Levels:           3  (IBUF=1 LUT6=2)
+  Clock Path Skew:        4.855ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W14                                               0.000     0.000 r  sw[6] (IN)
+                         net (fo=0)                   0.000     0.000    sw[6]
+    W14                  IBUF (Prop_ibuf_I_O)         1.450     1.450 r  sw_IBUF[6]_inst/O
+                         net (fo=1, routed)           1.619     3.069    btn3_pulse/sw_IBUF[6]
+    SLICE_X0Y14          LUT6 (Prop_lut6_I5_O)        0.124     3.193 r  btn3_pulse/FSM_sequential_state[2]_i_2/O
+                         net (fo=1, routed)           0.291     3.484    btnReset_pulse/FSM_sequential_state_reg[2]
+    SLICE_X1Y14          LUT6 (Prop_lut6_I1_O)        0.124     3.608 r  btnReset_pulse/FSM_sequential_state[2]_i_1/O
+                         net (fo=1, routed)           0.000     3.608    btnReset_pulse_n_1
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514     4.855    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[2]/C
+
+Slack:                    inf
+  Source:                 btnL
+                            (input port)
+  Destination:            btn2_pulse/q_signals_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        3.030ns  (logic 1.451ns (47.898%)  route 1.579ns (52.102%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.855ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W19                                               0.000     0.000 r  btnL (IN)
+                         net (fo=0)                   0.000     0.000    btnL
+    W19                  IBUF (Prop_ibuf_I_O)         1.451     1.451 r  btnL_IBUF_inst/O
+                         net (fo=1, routed)           1.579     3.030    btn2_pulse/D[0]
+    SLICE_X0Y13          FDRE                                         r  btn2_pulse/q_signals_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514     4.855    btn2_pulse/CLK
+    SLICE_X0Y13          FDRE                                         r  btn2_pulse/q_signals_reg[0]/C
+
+Slack:                    inf
+  Source:                 btnC
+                            (input port)
+  Destination:            btnReset_pulse/q_signals_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        2.503ns  (logic 1.441ns (57.577%)  route 1.062ns (42.423%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.855ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 r  btnC (IN)
+                         net (fo=0)                   0.000     0.000    btnC
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 r  btnC_IBUF_inst/O
+                         net (fo=1, routed)           1.062     2.503    btnReset_pulse/D[0]
+    SLICE_X0Y13          FDRE                                         r  btnReset_pulse/q_signals_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514     4.855    btnReset_pulse/CLK
+    SLICE_X0Y13          FDRE                                         r  btnReset_pulse/q_signals_reg[0]/C
+
+Slack:                    inf
+  Source:                 btnD
+                            (input port)
+  Destination:            btn1_pulse/q_signals_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        2.499ns  (logic 1.452ns (58.110%)  route 1.047ns (41.890%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.855ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U17                                               0.000     0.000 r  btnD (IN)
+                         net (fo=0)                   0.000     0.000    btnD
+    U17                  IBUF (Prop_ibuf_I_O)         1.452     1.452 r  btnD_IBUF_inst/O
+                         net (fo=1, routed)           1.047     2.499    btn1_pulse/D[0]
+    SLICE_X3Y14          FDRE                                         r  btn1_pulse/q_signals_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514     4.855    btn1_pulse/CLK
+    SLICE_X3Y14          FDRE                                         r  btn1_pulse/q_signals_reg[0]/C
+
+Slack:                    inf
+  Source:                 btnU
+                            (input port)
+  Destination:            btn3_pulse/q_signals_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        2.483ns  (logic 1.454ns (58.557%)  route 1.029ns (41.443%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.855ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    T18                                               0.000     0.000 r  btnU (IN)
+                         net (fo=0)                   0.000     0.000    btnU
+    T18                  IBUF (Prop_ibuf_I_O)         1.454     1.454 r  btnU_IBUF_inst/O
+                         net (fo=1, routed)           1.029     2.483    btn3_pulse/D[0]
+    SLICE_X3Y14          FDRE                                         r  btn3_pulse/q_signals_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514     4.855    btn3_pulse/CLK
+    SLICE_X3Y14          FDRE                                         r  btn3_pulse/q_signals_reg[0]/C
+
+Slack:                    inf
+  Source:                 btnR
+                            (input port)
+  Destination:            btn0_pulse/q_signals_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        2.450ns  (logic 1.451ns (59.236%)  route 0.999ns (40.764%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.855ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    T17                                               0.000     0.000 r  btnR (IN)
+                         net (fo=0)                   0.000     0.000    btnR
+    T17                  IBUF (Prop_ibuf_I_O)         1.451     1.451 r  btnR_IBUF_inst/O
+                         net (fo=1, routed)           0.999     2.450    btn0_pulse/D[0]
+    SLICE_X3Y14          FDRE                                         r  btn0_pulse/q_signals_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          1.514     4.855    btn0_pulse/CLK
+    SLICE_X3Y14          FDRE                                         r  btn0_pulse/q_signals_reg[0]/C
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 btnR
+                            (input port)
+  Destination:            btn0_pulse/q_signals_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.598ns  (logic 0.219ns (36.674%)  route 0.379ns (63.326%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.988ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    T17                                               0.000     0.000 r  btnR (IN)
+                         net (fo=0)                   0.000     0.000    btnR
+    T17                  IBUF (Prop_ibuf_I_O)         0.219     0.219 r  btnR_IBUF_inst/O
+                         net (fo=1, routed)           0.379     0.598    btn0_pulse/D[0]
+    SLICE_X3Y14          FDRE                                         r  btn0_pulse/q_signals_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn0_pulse/CLK
+    SLICE_X3Y14          FDRE                                         r  btn0_pulse/q_signals_reg[0]/C
+
+Slack:                    inf
+  Source:                 btnC
+                            (input port)
+  Destination:            btnReset_pulse/q_signals_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.605ns  (logic 0.210ns (34.605%)  route 0.396ns (65.395%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.988ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 r  btnC (IN)
+                         net (fo=0)                   0.000     0.000    btnC
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 r  btnC_IBUF_inst/O
+                         net (fo=1, routed)           0.396     0.605    btnReset_pulse/D[0]
+    SLICE_X0Y13          FDRE                                         r  btnReset_pulse/q_signals_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btnReset_pulse/CLK
+    SLICE_X0Y13          FDRE                                         r  btnReset_pulse/q_signals_reg[0]/C
+
+Slack:                    inf
+  Source:                 btnU
+                            (input port)
+  Destination:            btn3_pulse/q_signals_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.616ns  (logic 0.222ns (36.033%)  route 0.394ns (63.967%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.988ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    T18                                               0.000     0.000 r  btnU (IN)
+                         net (fo=0)                   0.000     0.000    btnU
+    T18                  IBUF (Prop_ibuf_I_O)         0.222     0.222 r  btnU_IBUF_inst/O
+                         net (fo=1, routed)           0.394     0.616    btn3_pulse/D[0]
+    SLICE_X3Y14          FDRE                                         r  btn3_pulse/q_signals_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn3_pulse/CLK
+    SLICE_X3Y14          FDRE                                         r  btn3_pulse/q_signals_reg[0]/C
+
+Slack:                    inf
+  Source:                 btnD
+                            (input port)
+  Destination:            btn1_pulse/q_signals_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.632ns  (logic 0.221ns (34.921%)  route 0.411ns (65.079%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.988ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U17                                               0.000     0.000 r  btnD (IN)
+                         net (fo=0)                   0.000     0.000    btnD
+    U17                  IBUF (Prop_ibuf_I_O)         0.221     0.221 r  btnD_IBUF_inst/O
+                         net (fo=1, routed)           0.411     0.632    btn1_pulse/D[0]
+    SLICE_X3Y14          FDRE                                         r  btn1_pulse/q_signals_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn1_pulse/CLK
+    SLICE_X3Y14          FDRE                                         r  btn1_pulse/q_signals_reg[0]/C
+
+Slack:                    inf
+  Source:                 btnL
+                            (input port)
+  Destination:            btn2_pulse/q_signals_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.831ns  (logic 0.219ns (26.398%)  route 0.612ns (73.602%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.988ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W19                                               0.000     0.000 r  btnL (IN)
+                         net (fo=0)                   0.000     0.000    btnL
+    W19                  IBUF (Prop_ibuf_I_O)         0.219     0.219 r  btnL_IBUF_inst/O
+                         net (fo=1, routed)           0.612     0.831    btn2_pulse/D[0]
+    SLICE_X0Y13          FDRE                                         r  btn2_pulse/q_signals_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    btn2_pulse/CLK
+    SLICE_X0Y13          FDRE                                         r  btn2_pulse/q_signals_reg[0]/C
+
+Slack:                    inf
+  Source:                 sw[2]
+                            (input port)
+  Destination:            FSM_sequential_state_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.841ns  (logic 0.322ns (38.253%)  route 0.519ns (61.747%))
+  Logic Levels:           3  (IBUF=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        1.988ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W16                                               0.000     0.000 r  sw[2] (IN)
+                         net (fo=0)                   0.000     0.000    sw[2]
+    W16                  IBUF (Prop_ibuf_I_O)         0.232     0.232 r  sw_IBUF[2]_inst/O
+                         net (fo=1, routed)           0.393     0.625    btn3_pulse/sw_IBUF[2]
+    SLICE_X2Y13          LUT6 (Prop_lut6_I5_O)        0.045     0.670 r  btn3_pulse/FSM_sequential_state[1]_i_2/O
+                         net (fo=1, routed)           0.126     0.796    btn3_pulse/FSM_sequential_state[1]_i_2_n_0
+    SLICE_X1Y14          LUT5 (Prop_lut5_I2_O)        0.045     0.841 r  btn3_pulse/FSM_sequential_state[1]_i_1/O
+                         net (fo=1, routed)           0.000     0.841    btn3_pulse_n_1
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[1]/C
+
+Slack:                    inf
+  Source:                 sw[7]
+                            (input port)
+  Destination:            FSM_sequential_state_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.951ns  (logic 0.317ns (33.322%)  route 0.634ns (66.678%))
+  Logic Levels:           3  (IBUF=1 LUT6=2)
+  Clock Path Skew:        1.988ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W13                                               0.000     0.000 r  sw[7] (IN)
+                         net (fo=0)                   0.000     0.000    sw[7]
+    W13                  IBUF (Prop_ibuf_I_O)         0.227     0.227 r  sw_IBUF[7]_inst/O
+                         net (fo=1, routed)           0.529     0.756    btn3_pulse/sw_IBUF[7]
+    SLICE_X0Y14          LUT6 (Prop_lut6_I1_O)        0.045     0.801 r  btn3_pulse/FSM_sequential_state[2]_i_2/O
+                         net (fo=1, routed)           0.105     0.906    btnReset_pulse/FSM_sequential_state_reg[2]
+    SLICE_X1Y14          LUT6 (Prop_lut6_I1_O)        0.045     0.951 r  btnReset_pulse/FSM_sequential_state[2]_i_1/O
+                         net (fo=1, routed)           0.000     0.951    btnReset_pulse_n_1
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[2]/C
+
+Slack:                    inf
+  Source:                 sw[5]
+                            (input port)
+  Destination:            FSM_sequential_state_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        1.010ns  (logic 0.324ns (32.080%)  route 0.686ns (67.920%))
+  Logic Levels:           3  (IBUF=1 LUT6=2)
+  Clock Path Skew:        1.988ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.988ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    V15                                               0.000     0.000 r  sw[5] (IN)
+                         net (fo=0)                   0.000     0.000    sw[5]
+    V15                  IBUF (Prop_ibuf_I_O)         0.234     0.234 r  sw_IBUF[5]_inst/O
+                         net (fo=1, routed)           0.527     0.761    btn3_pulse/sw_IBUF[5]
+    SLICE_X2Y13          LUT6 (Prop_lut6_I0_O)        0.045     0.806 r  btn3_pulse/FSM_sequential_state[1]_i_3/O
+                         net (fo=2, routed)           0.159     0.965    btn3_pulse/FSM_sequential_state[1]_i_3_n_0
+    SLICE_X1Y14          LUT6 (Prop_lut6_I4_O)        0.045     1.010 r  btn3_pulse/FSM_sequential_state[0]_i_1/O
+                         net (fo=1, routed)           0.000     1.010    btn3_pulse_n_0
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=53, routed)          0.861     1.988    clk_IBUF_BUFG
+    SLICE_X1Y14          FDRE                                         r  FSM_sequential_state_reg[0]/C
+
+
+
+
+
diff --git a/tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.pb b/tp5_n/tp5_n.runs/impl_1/digi_code_utilization_placed.pb
similarity index 53%
rename from tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.pb
rename to tp5_n/tp5_n.runs/impl_1/digi_code_utilization_placed.pb
index dd8c36659fc8375eca6c825386eb31c600af0549..66374b2ddda4b8c35535083ba70be4a3e5719789 100644
Binary files a/tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.pb and b/tp5_n/tp5_n.runs/impl_1/digi_code_utilization_placed.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/digi_code_utilization_placed.rpt b/tp5_n/tp5_n.runs/impl_1/digi_code_utilization_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..dea3ee0adb9f298ee48c7924e13151f2bbbe339f
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/digi_code_utilization_placed.rpt
@@ -0,0 +1,216 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 11:03:16 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_utilization -file digi_code_utilization_placed.rpt -pb digi_code_utilization_placed.pb
+| Design       : digi_code
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+|        Site Type        | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs              |   19 |     0 |          0 |     20800 |  0.09 |
+|   LUT as Logic          |   19 |     0 |          0 |     20800 |  0.09 |
+|   LUT as Memory         |    0 |     0 |          0 |      9600 |  0.00 |
+| Slice Registers         |   53 |     0 |          0 |     41600 |  0.13 |
+|   Register as Flip Flop |   53 |     0 |          0 |     41600 |  0.13 |
+|   Register as Latch     |    0 |     0 |          0 |     41600 |  0.00 |
+| F7 Muxes                |    0 |     0 |          0 |     16300 |  0.00 |
+| F8 Muxes                |    0 |     0 |          0 |      8150 |  0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 0     |          Yes |         Set |            - |
+| 53    |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+------+-------+------------+-----------+-------+
+|                  Site Type                 | Used | Fixed | Prohibited | Available | Util% |
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Slice                                      |   16 |     0 |          0 |      8150 |  0.20 |
+|   SLICEL                                   |   14 |     0 |            |           |       |
+|   SLICEM                                   |    2 |     0 |            |           |       |
+| LUT as Logic                               |   19 |     0 |          0 |     20800 |  0.09 |
+|   using O5 output only                     |    0 |       |            |           |       |
+|   using O6 output only                     |   18 |       |            |           |       |
+|   using O5 and O6                          |    1 |       |            |           |       |
+| LUT as Memory                              |    0 |     0 |          0 |      9600 |  0.00 |
+|   LUT as Distributed RAM                   |    0 |     0 |            |           |       |
+|     using O5 output only                   |    0 |       |            |           |       |
+|     using O6 output only                   |    0 |       |            |           |       |
+|     using O5 and O6                        |    0 |       |            |           |       |
+|   LUT as Shift Register                    |    0 |     0 |            |           |       |
+|     using O5 output only                   |    0 |       |            |           |       |
+|     using O6 output only                   |    0 |       |            |           |       |
+|     using O5 and O6                        |    0 |       |            |           |       |
+| Slice Registers                            |   53 |     0 |          0 |     41600 |  0.13 |
+|   Register driven from within the Slice    |   36 |       |            |           |       |
+|   Register driven from outside the Slice   |   17 |       |            |           |       |
+|     LUT in front of the register is unused |   14 |       |            |           |       |
+|     LUT in front of the register is used   |    3 |       |            |           |       |
+| Unique Control Sets                        |    2 |       |          0 |      8150 |  0.02 |
++--------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile |    0 |     0 |          0 |        50 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |          0 |        50 |  0.00 |
+|   RAMB18       |    0 |     0 |          0 |       100 |  0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |        90 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |   16 |    16 |          0 |       106 | 15.09 |
+|   IOB Master Pads           |    7 |       |            |           |       |
+|   IOB Slave Pads            |    9 |       |            |           |       |
+| Bonded IPADs                |    0 |     0 |          0 |        10 |  0.00 |
+| Bonded OPADs                |    0 |     0 |          0 |         4 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |         5 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |         5 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |        20 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |        20 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |          0 |         5 |  0.00 |
+| IBUFDS                      |    0 |     0 |          0 |       104 |  0.00 |
+| GTPE2_CHANNEL               |    0 |     0 |          0 |         2 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |        20 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |        20 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |          0 |       250 |  0.00 |
+| IBUFDS_GTE2                 |    0 |     0 |          0 |         2 |  0.00 |
+| ILOGIC                      |    0 |     0 |          0 |       106 |  0.00 |
+| OLOGIC                      |    0 |     0 |          0 |       106 |  0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+|  Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL   |    1 |     0 |          0 |        32 |  3.13 |
+| BUFIO      |    0 |     0 |          0 |        20 |  0.00 |
+| MMCME2_ADV |    0 |     0 |          0 |         5 |  0.00 |
+| PLLE2_ADV  |    0 |     0 |          0 |         5 |  0.00 |
+| BUFMRCE    |    0 |     0 |          0 |        10 |  0.00 |
+| BUFHCE     |    0 |     0 |          0 |        72 |  0.00 |
+| BUFR       |    0 |     0 |          0 |        20 |  0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |          0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDRE     |   53 |        Flop & Latch |
+| IBUF     |   14 |                  IO |
+| LUT3     |   10 |                 LUT |
+| CARRY4   |   10 |          CarryLogic |
+| LUT6     |    7 |                 LUT |
+| OBUF     |    2 |                  IO |
+| LUT5     |    1 |                 LUT |
+| LUT2     |    1 |                 LUT |
+| LUT1     |    1 |                 LUT |
+| BUFG     |    1 |               Clock |
++----------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/tp5_n/tp5_n.runs/impl_1/gen_run.xml b/tp5_n/tp5_n.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..d9bdba8d0f8e33fbe0484d90b83fc67b1c70f37a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/gen_run.xml
@@ -0,0 +1,146 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1745917256">
+  <File Type="PA-TCL" Name="digi_code.tcl"/>
+  <File Type="REPORTS-TCL" Name="digi_code_reports.tcl"/>
+  <File Type="INIT-TIMING" Name="digi_code_timing_summary_init.rpt"/>
+  <File Type="OPT-DCP" Name="digi_code_opt.dcp"/>
+  <File Type="OPT-DRC" Name="digi_code_drc_opted.rpt"/>
+  <File Type="OPT-METHODOLOGY-DRC" Name="digi_code_methodology_drc_opted.rpt"/>
+  <File Type="OPT-HWDEF" Name="digi_code.hwdef"/>
+  <File Type="OPT-TIMING" Name="digi_code_timing_summary_opted.rpt"/>
+  <File Type="OPT-RQA-PB" Name="digi_code_rqa_opted.pb"/>
+  <File Type="PWROPT-DCP" Name="digi_code_pwropt.dcp"/>
+  <File Type="PWROPT-DRC" Name="digi_code_drc_pwropted.rpt"/>
+  <File Type="PWROPT-TIMING" Name="digi_code_timing_summary_pwropted.rpt"/>
+  <File Type="PLACE-DCP" Name="digi_code_placed.dcp"/>
+  <File Type="PLACE-IO" Name="digi_code_io_placed.rpt"/>
+  <File Type="PLACE-CLK" Name="digi_code_clock_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL" Name="digi_code_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL-PB" Name="digi_code_utilization_placed.pb"/>
+  <File Type="PLACE-CTRL" Name="digi_code_control_sets_placed.rpt"/>
+  <File Type="PLACE-SIMILARITY" Name="digi_code_incremental_reuse_placed.rpt"/>
+  <File Type="PLACE-PRE-SIMILARITY" Name="digi_code_incremental_reuse_pre_placed.rpt"/>
+  <File Type="PLACE-TIMING" Name="digi_code_timing_summary_placed.rpt"/>
+  <File Type="PLACE-RQA-PB" Name="digi_code_rqa_placed.pb"/>
+  <File Type="POSTPLACE-PWROPT-DCP" Name="digi_code_postplace_pwropt.dcp"/>
+  <File Type="POSTPLACE-PWROPT-TIMING" Name="digi_code_timing_summary_postplace_pwropted.rpt"/>
+  <File Type="PHYSOPT-DCP" Name="digi_code_physopt.dcp"/>
+  <File Type="PHYSOPT-DRC" Name="digi_code_drc_physopted.rpt"/>
+  <File Type="PHYSOPT-TIMING" Name="digi_code_timing_summary_physopted.rpt"/>
+  <File Type="ROUTE-ERROR-DCP" Name="digi_code_routed_error.dcp"/>
+  <File Type="ROUTE-DCP" Name="digi_code_routed.dcp"/>
+  <File Type="ROUTE-BLACKBOX-DCP" Name="digi_code_routed_bb.dcp"/>
+  <File Type="ROUTE-DRC" Name="digi_code_drc_routed.rpt"/>
+  <File Type="ROUTE-DRC-PB" Name="digi_code_drc_routed.pb"/>
+  <File Type="ROUTE-DRC-RPX" Name="digi_code_drc_routed.rpx"/>
+  <File Type="ROUTE-METHODOLOGY-DRC" Name="digi_code_methodology_drc_routed.rpt"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="digi_code_methodology_drc_routed.rpx"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="digi_code_methodology_drc_routed.pb"/>
+  <File Type="ROUTE-PWR" Name="digi_code_power_routed.rpt"/>
+  <File Type="ROUTE-PWR-SUM" Name="digi_code_power_summary_routed.pb"/>
+  <File Type="ROUTE-PWR-RPX" Name="digi_code_power_routed.rpx"/>
+  <File Type="ROUTE-STATUS" Name="digi_code_route_status.rpt"/>
+  <File Type="ROUTE-STATUS-PB" Name="digi_code_route_status.pb"/>
+  <File Type="ROUTE-TIMINGSUMMARY" Name="digi_code_timing_summary_routed.rpt"/>
+  <File Type="ROUTE-TIMING-PB" Name="digi_code_timing_summary_routed.pb"/>
+  <File Type="ROUTE-TIMING-RPX" Name="digi_code_timing_summary_routed.rpx"/>
+  <File Type="ROUTE-SIMILARITY" Name="digi_code_incremental_reuse_routed.rpt"/>
+  <File Type="ROUTE-CLK" Name="digi_code_clock_utilization_routed.rpt"/>
+  <File Type="ROUTE-BUS-SKEW" Name="digi_code_bus_skew_routed.rpt"/>
+  <File Type="ROUTE-BUS-SKEW-PB" Name="digi_code_bus_skew_routed.pb"/>
+  <File Type="ROUTE-BUS-SKEW-RPX" Name="digi_code_bus_skew_routed.rpx"/>
+  <File Type="ROUTE-RQS-PB" Name="digi_code_rqs_routed.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-DCP" Name="digi_code_postroute_physopt.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="digi_code_postroute_physopt_bb.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="digi_code_timing_summary_postroute_physopted.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="digi_code_timing_summary_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="digi_code_timing_summary_postroute_physopted.rpx"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="digi_code_bus_skew_postroute_physopted.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="digi_code_bus_skew_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="digi_code_bus_skew_postroute_physopted.rpx"/>
+  <File Type="BG-BIT" Name="digi_code.bit"/>
+  <File Type="BG-BIN" Name="digi_code.bin"/>
+  <File Type="BITSTR-MSK" Name="digi_code.msk"/>
+  <File Type="BITSTR-RBT" Name="digi_code.rbt"/>
+  <File Type="BITSTR-NKY" Name="digi_code.nky"/>
+  <File Type="BITSTR-BMM" Name="digi_code_bd.bmm"/>
+  <File Type="BITSTR-MMI" Name="digi_code.mmi"/>
+  <File Type="PDI-FILE" Name="digi_code.pdi"/>
+  <File Type="BOOT-PDI-FILE" Name="digi_code_boot.pdi"/>
+  <File Type="PL-PDI-FILE" Name="digi_code_pld.pdi"/>
+  <File Type="RCFI_FILE" Name="digi_code.rcfi"/>
+  <File Type="CFI_FILE" Name="digi_code.cfi"/>
+  <File Type="RNPI_FILE" Name="digi_code.rnpi"/>
+  <File Type="NPI_FILE" Name="digi_code.npi"/>
+  <File Type="RBD_FILE" Name="digi_code.rbd"/>
+  <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+  <File Type="BITSTR-LTX" Name="digi_code.ltx"/>
+  <File Type="BITSTR-SYSDEF" Name="digi_code.sysdef"/>
+  <File Type="BG-BGN" Name="digi_code.bgn"/>
+  <File Type="BG-DRC" Name="digi_code.drc"/>
+  <File Type="RDI-RDI" Name="digi_code.vdi"/>
+  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+  <File Type="ROUTE-RQS" Name="digi_code_routed.rqs"/>
+  <File Type="POSTROUTE-PHYSOPT-RQS" Name="digi_code_postroute_physopted.rqs"/>
+  <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PSRCDIR/sources_1/new/digi_code.vhd">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../Documents/HD/hardware_design/tp5/tp5.srcs/sources_1/new/digi_code.vhd"/>
+        <Attr Name="ImportTime" Val="1745321700"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/new/anti_rebond.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/new/Enable190.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="digi_code"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys3_Master.xdc">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../Documents/HD/hardware_design/tp_3/tp_3.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc"/>
+        <Attr Name="ImportTime" Val="1743511343"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+    <Filter Type="Utils"/>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
+    <Step Id="init_design"/>
+    <Step Id="opt_design"/>
+    <Step Id="power_opt_design"/>
+    <Step Id="place_design"/>
+    <Step Id="post_place_power_opt_design"/>
+    <Step Id="phys_opt_design"/>
+    <Step Id="route_design"/>
+    <Step Id="post_route_phys_opt_design"/>
+    <Step Id="write_bitstream"/>
+  </Strategy>
+</GenRun>
diff --git a/tp5_n/tp5_n.runs/impl_1/htr.txt b/tp5_n/tp5_n.runs/impl_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..1142df83a9ec021ba93dd3876f300249db46793c
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/htr.txt
@@ -0,0 +1,10 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+
+vivado -log digi_code.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source digi_code.tcl -notrace
diff --git a/tp5_n/tp5_n.runs/impl_1/init_design.pb b/tp5_n/tp5_n.runs/impl_1/init_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..32621bd1588c0c5be8e5c540bd94cd08afc675a8
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diff --git a/tp5_n/tp5_n.runs/impl_1/opt_design.pb b/tp5_n/tp5_n.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..9c569cc1ce207b5690ed49367d5f509a137ce88f
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/opt_design.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/phys_opt_design.pb b/tp5_n/tp5_n.runs/impl_1/phys_opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..bbab5c20d44bd01b9e09de19972a877f636d4568
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/phys_opt_design.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/place_design.pb b/tp5_n/tp5_n.runs/impl_1/place_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..a2f2ef95a233549ab00d5cf59f55792f29da5a43
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/place_design.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/route_design.pb b/tp5_n/tp5_n.runs/impl_1/route_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3b0ef2f8fa974b340736ed31138e5491438091f7
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/route_design.pb differ
diff --git a/tp5_n/tp5_n.runs/impl_1/vivado.jou b/tp5_n/tp5_n.runs/impl_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..9046aca1ef8cdea42c3ce49432d55ec5db7519f7
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Apr 29 11:02:11 2025
+# Process ID         : 18068
+# Current directory  : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1
+# Command line       : vivado.exe -log digi_code.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source digi_code.tcl -notrace
+# Log file           : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code.vdi
+# Journal file       : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1\vivado.jou
+# Running On         : LAPTOP-RU5MPQFG
+# Platform           : Windows Server 2016 or Windows 10
+# Operating System   : 26100
+# Processor Detail   : AMD Ryzen 5 5500U with Radeon Graphics         
+# CPU Frequency      : 2096 MHz
+# CPU Physical cores : 6
+# CPU Logical cores  : 12
+# Host memory        : 16468 MB
+# Swap memory        : 1073 MB
+# Total Virtual      : 17542 MB
+# Available Virtual  : 8793 MB
+#-----------------------------------------------------------
+source digi_code.tcl -notrace
diff --git a/tp5_n/tp5_n.runs/impl_1/vivado.pb b/tp5_n/tp5_n.runs/impl_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..18234fe433d119d3b911167b93f5319177b29d4c
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diff --git a/tp5_n/tp5_n.runs/impl_1/vivado_2948.backup.jou b/tp5_n/tp5_n.runs/impl_1/vivado_2948.backup.jou
new file mode 100644
index 0000000000000000000000000000000000000000..95fbbac7ad18b92a1d0a9db63b0d71228cfe6a4a
--- /dev/null
+++ b/tp5_n/tp5_n.runs/impl_1/vivado_2948.backup.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Apr 29 08:54:05 2025
+# Process ID         : 2948
+# Current directory  : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1
+# Command line       : vivado.exe -log digi_code.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source digi_code.tcl -notrace
+# Log file           : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1/digi_code.vdi
+# Journal file       : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/impl_1\vivado.jou
+# Running On         : LAPTOP-RU5MPQFG
+# Platform           : Windows Server 2016 or Windows 10
+# Operating System   : 26100
+# Processor Detail   : AMD Ryzen 5 5500U with Radeon Graphics         
+# CPU Frequency      : 2096 MHz
+# CPU Physical cores : 6
+# CPU Logical cores  : 12
+# Host memory        : 16468 MB
+# Swap memory        : 1073 MB
+# Total Virtual      : 17542 MB
+# Available Virtual  : 9038 MB
+#-----------------------------------------------------------
+source digi_code.tcl -notrace
diff --git a/tp5_n/tp5_n.runs/impl_1/write_bitstream.pb b/tp5_n/tp5_n.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000000000000000000000000000000000000..ae69c46002073dd756c9f02809bfea7eb28adad2
Binary files /dev/null and b/tp5_n/tp5_n.runs/impl_1/write_bitstream.pb differ
diff --git a/tp5_n/tp5_n.runs/synth_1/.Xil/anti_rebond_propImpl.xdc b/tp5_n/tp5_n.runs/synth_1/.Xil/anti_rebond_propImpl.xdc
deleted file mode 100644
index 95f43f158aab560fcd4ca52d0acd0d5dff77cf46..0000000000000000000000000000000000000000
--- a/tp5_n/tp5_n.runs/synth_1/.Xil/anti_rebond_propImpl.xdc
+++ /dev/null
@@ -1,63 +0,0 @@
-set_property SRC_FILE_INFO {cfile:/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc rfile:../../../tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc id:1} [current_design]
-set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W5 [get_ports clk]
-set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
-set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
-set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
-set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
-set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
-set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
-set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
-set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
-set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
-set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
-set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
-set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
-set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
-set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
-set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
-set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
-set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U16 [get_ports {led[0]}]
-set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
-set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN E19 [get_ports {led[1]}]
-set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
-set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U18 [get_ports btnC]
-set_property src_info {type:XDC file:1 line:112 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports btnC]
-set_property src_info {type:XDC file:1 line:113 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN T18 [get_ports btnU]
-set_property src_info {type:XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports btnU]
-set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W19 [get_ports btnL]
-set_property src_info {type:XDC file:1 line:116 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports btnL]
-set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN T17 [get_ports btnR]
-set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports btnR]
-set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U17 [get_ports btnD]
-set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design]
-set_property IOSTANDARD LVCMOS33 [get_ports btnD]
diff --git a/tp5_n/tp5_n.runs/synth_1/.Xil/digi_code_propImpl.xdc b/tp5_n/tp5_n.runs/synth_1/.Xil/digi_code_propImpl.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..cb4920266605d29f7c7cdf52850268a9f5881245
--- /dev/null
+++ b/tp5_n/tp5_n.runs/synth_1/.Xil/digi_code_propImpl.xdc
@@ -0,0 +1,33 @@
+set_property SRC_FILE_INFO {cfile:C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc rfile:../../../tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W5 [get_ports clk]
+set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
+set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
+set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
+set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
+set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
+set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
+set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
+set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
+set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U16 [get_ports {led[0]}]
+set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN E19 [get_ports {led[1]}]
+set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U18 [get_ports btnC]
+set_property src_info {type:XDC file:1 line:113 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T18 [get_ports btnU]
+set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W19 [get_ports btnL]
+set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T17 [get_ports btnR]
+set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U17 [get_ports btnD]
diff --git a/tp5_n/tp5_n.runs/synth_1/anti_rebond.dcp b/tp5_n/tp5_n.runs/synth_1/anti_rebond.dcp
deleted file mode 100644
index 7f59ccdf46eaaecf0f9a212652b1729ede3746c5..0000000000000000000000000000000000000000
Binary files a/tp5_n/tp5_n.runs/synth_1/anti_rebond.dcp and /dev/null differ
diff --git a/tp5_n/tp5_n.runs/synth_1/anti_rebond.vds b/tp5_n/tp5_n.runs/synth_1/anti_rebond.vds
deleted file mode 100644
index 93452fdb418ba759d37b572e7c03edcfa1f2d540..0000000000000000000000000000000000000000
--- a/tp5_n/tp5_n.runs/synth_1/anti_rebond.vds
+++ /dev/null
@@ -1,296 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2021.1 (64-bit)
-# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
-# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
-# Start of session at: Tue Apr 22 16:16:17 2025
-# Process ID: 497770
-# Current directory: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1
-# Command line: vivado -log anti_rebond.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source anti_rebond.tcl
-# Log file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/anti_rebond.vds
-# Journal file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/vivado.jou
-#-----------------------------------------------------------
-source anti_rebond.tcl -notrace
-Command: synth_design -top anti_rebond -part xc7a35tcpg236-1
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
-INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
-INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 497841
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2448.441 ; gain = 0.000 ; free physical = 578 ; free virtual = 7792
----------------------------------------------------------------------------------
-INFO: [Synth 8-638] synthesizing module 'anti_rebond' [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:43]
-INFO: [Synth 8-256] done synthesizing module 'anti_rebond' (1#1) [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:43]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2448.441 ; gain = 0.000 ; free physical = 220 ; free virtual = 6899
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2448.441 ; gain = 0.000 ; free physical = 203 ; free virtual = 6883
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2448.441 ; gain = 0.000 ; free physical = 203 ; free virtual = 6883
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2448.441 ; gain = 0.000 ; free physical = 198 ; free virtual = 6877
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
-WARNING: [Vivado 12-584] No ports matched 'sw[0]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:12]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:12]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[0]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:13]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:13]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[1]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:14]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:14]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[1]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:15]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:15]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[2]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:16]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:16]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[2]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:17]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:17]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[3]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:18]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:18]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[3]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:19]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:19]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[4]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:20]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:20]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[4]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:21]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:21]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[5]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:22]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:22]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[5]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:23]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:23]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[6]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:24]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:24]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[6]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:25]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:25]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[7]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:26]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:26]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'sw[7]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:27]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:27]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'led[0]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:47]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:47]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'led[0]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:48]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:48]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'led[1]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:49]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:49]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'led[1]'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:50]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:50]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'btnC'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:111]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:111]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'btnC'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:112]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:112]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'btnU'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:113]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:113]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'btnU'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:114]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:114]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'btnL'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:115]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:115]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'btnL'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:116]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:116]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'btnR'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:117]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:117]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'btnR'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:118]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:118]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'btnD'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:119]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:119]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-WARNING: [Vivado 12-584] No ports matched 'btnD'. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:120]
-CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:120]
-Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
-Finished Parsing XDC File [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/anti_rebond_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/anti_rebond_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2496.309 ; gain = 0.000 ; free physical = 921 ; free virtual = 7610
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2496.309 ; gain = 0.000 ; free physical = 919 ; free virtual = 7609
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 984 ; free virtual = 7674
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7a35tcpg236-1
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 987 ; free virtual = 7676
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 987 ; free virtual = 7676
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 975 ; free virtual = 7666
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start RTL Component Statistics 
----------------------------------------------------------------------------------
-Detailed RTL Component Info : 
-+---Registers : 
-	                6 Bit    Registers := 1     
-	                1 Bit    Registers := 1     
----------------------------------------------------------------------------------
-Finished RTL Component Statistics 
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 90 (col length:60)
-BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 963 ; free virtual = 7657
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 845 ; free virtual = 7537
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 845 ; free virtual = 7537
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 836 ; free virtual = 7528
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-Report BlackBoxes: 
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage: 
-+------+-----+------+
-|      |Cell |Count |
-+------+-----+------+
-|1     |BUFG |     1|
-|2     |LUT3 |     4|
-|3     |FDRE |     7|
-|4     |IBUF |     3|
-|5     |OBUF |     1|
-+------+-----+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 831 ; free virtual = 7526
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2496.309 ; gain = 0.000 ; free physical = 885 ; free virtual = 7580
-Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2496.309 ; gain = 47.867 ; free physical = 883 ; free virtual = 7578
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2496.309 ; gain = 0.000 ; free physical = 879 ; free virtual = 7574
-INFO: [Project 1-570] Preparing netlist for logic optimization
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2496.309 ; gain = 0.000 ; free physical = 913 ; free virtual = 7608
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Synth Design complete, checksum: dc892547
-INFO: [Common 17-83] Releasing license: Synthesis
-15 Infos, 30 Warnings, 30 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:16 . Memory (MB): peak = 2496.309 ; gain = 48.023 ; free physical = 1065 ; free virtual = 7760
-INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
-INFO: [Common 17-1381] The checkpoint '/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/anti_rebond.dcp' has been generated.
-INFO: [runtcl-4] Executing : report_utilization -file anti_rebond_utilization_synth.rpt -pb anti_rebond_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Tue Apr 22 16:16:41 2025...
diff --git a/tp5_n/tp5_n.runs/synth_1/digi_code.dcp b/tp5_n/tp5_n.runs/synth_1/digi_code.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..d88dac3e71cd51a6324ecb57619938af1d130cfe
Binary files /dev/null and b/tp5_n/tp5_n.runs/synth_1/digi_code.dcp differ
diff --git a/tp5_n/tp5_n.runs/synth_1/digi_code.tcl b/tp5_n/tp5_n.runs/synth_1/digi_code.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b2efeb37dda97fde815fdcc480df5ee3307914d8
--- /dev/null
+++ b/tp5_n/tp5_n.runs/synth_1/digi_code.tcl
@@ -0,0 +1,113 @@
+# 
+# Synthesis run script generated by Vivado
+# 
+
+set TIME_start [clock seconds] 
+namespace eval ::optrace {
+  variable script "C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1/digi_code.tcl"
+  variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+  namespace eval ::dispatch {
+    variable connected false
+    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+      set result "true"
+      if {[catch {
+        if {[lsearch -exact [package names] DispatchTcl] < 0} {
+          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
+        }
+        if {$result eq "false"} {
+          puts "WARNING: Could not load dispatch client library"
+        }
+        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+        if { $connect_id eq "" } {
+          puts "WARNING: Could not initialize dispatch client"
+        } else {
+          puts "INFO: Dispatch client connection id - $connect_id"
+          set connected true
+        }
+      } catch_res]} {
+        puts "WARNING: failed to connect to dispatch server - $catch_res"
+      }
+    }
+  }
+}
+if {$::dispatch::connected} {
+  # Remove the dummy proc if it exists.
+  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+    rename ::OPTRACE ""
+  }
+  proc ::OPTRACE { task action {tags {} } } {
+    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+  }
+  # dispatch is generic. We specifically want to attach logging.
+  ::vitis_log::connect_client
+} else {
+  # Add dummy proc if it doesn't exist.
+  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+        # Do nothing
+    }
+  }
+}
+
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+set_param chipscope.maxJobs 3
+set_param xicom.use_bs_reader 1
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a35tcpg236-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.cache/wt [current_project]
+set_property parent.project_path C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property ip_output_repo c:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_vhdl -library xil_defaultlib {
+  C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd
+  C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd
+  C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd
+}
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+  set_property used_in_implementation false $dcp
+}
+read_xdc C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc
+set_property used_in_implementation false [get_files C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top digi_code -part xc7a35tcpg236-1
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef digi_code.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+generate_parallel_reports -reports { "report_utilization -file digi_code_utilization_synth.rpt -pb digi_code_utilization_synth.pb"  } 
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/tp5_n/tp5_n.runs/synth_1/digi_code.vds b/tp5_n/tp5_n.runs/synth_1/digi_code.vds
new file mode 100644
index 0000000000000000000000000000000000000000..7612f58cfcdaf220e3ad0e57372053b64a9073fa
--- /dev/null
+++ b/tp5_n/tp5_n.runs/synth_1/digi_code.vds
@@ -0,0 +1,257 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Apr 29 11:01:00 2025
+# Process ID         : 7304
+# Current directory  : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1
+# Command line       : vivado.exe -log digi_code.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source digi_code.tcl
+# Log file           : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1/digi_code.vds
+# Journal file       : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1\vivado.jou
+# Running On         : LAPTOP-RU5MPQFG
+# Platform           : Windows Server 2016 or Windows 10
+# Operating System   : 26100
+# Processor Detail   : AMD Ryzen 5 5500U with Radeon Graphics         
+# CPU Frequency      : 2096 MHz
+# CPU Physical cores : 6
+# CPU Logical cores  : 12
+# Host memory        : 16468 MB
+# Swap memory        : 1073 MB
+# Total Virtual      : 17542 MB
+# Available Virtual  : 8688 MB
+#-----------------------------------------------------------
+source digi_code.tcl -notrace
+Command: synth_design -top digi_code -part xc7a35tcpg236-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 10712
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 989.836 ; gain = 466.688
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'digi_code' [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd:45]
+INFO: [Synth 8-3491] module 'clkdiv' declared at 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd:34' bound to instance 'clk_divide' of component 'clkdiv' [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd:77]
+INFO: [Synth 8-638] synthesizing module 'clkdiv' [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd:42]
+INFO: [Synth 8-256] done synthesizing module 'clkdiv' (0#1) [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd:42]
+INFO: [Synth 8-3491] module 'anti_rebond' declared at 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:34' bound to instance 'btn2_pulse' of component 'anti_rebond' [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd:84]
+INFO: [Synth 8-638] synthesizing module 'anti_rebond' [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:42]
+INFO: [Synth 8-256] done synthesizing module 'anti_rebond' (0#1) [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:42]
+INFO: [Synth 8-3491] module 'anti_rebond' declared at 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:34' bound to instance 'btn1_pulse' of component 'anti_rebond' [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd:91]
+INFO: [Synth 8-3491] module 'anti_rebond' declared at 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:34' bound to instance 'btn3_pulse' of component 'anti_rebond' [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd:98]
+INFO: [Synth 8-3491] module 'anti_rebond' declared at 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:34' bound to instance 'btn0_pulse' of component 'anti_rebond' [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd:105]
+INFO: [Synth 8-3491] module 'anti_rebond' declared at 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd:34' bound to instance 'btnReset_pulse' of component 'anti_rebond' [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd:112]
+WARNING: [Synth 8-614] signal 'sw' is read in the process but is not in the sensitivity list [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd:160]
+WARNING: [Synth 8-614] signal 'btnC_pulse' is read in the process but is not in the sensitivity list [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd:160]
+INFO: [Synth 8-256] done synthesizing module 'digi_code' (0#1) [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd:45]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1095.094 ; gain = 571.945
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1095.094 ; gain = 571.945
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1095.094 ; gain = 571.945
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1095.094 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+Finished Parsing XDC File [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/digi_code_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/digi_code_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1179.812 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1179.812 ; gain = 0.000
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1179.812 ; gain = 656.664
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a35tcpg236-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1179.812 ; gain = 656.664
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1179.812 ; gain = 656.664
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'digi_code'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+                      s0 |                              000 |                              000
+                      s1 |                              001 |                              001
+                      s2 |                              010 |                              010
+                      s3 |                              011 |                              011
+                   opend |                              100 |                              100
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'digi_code'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1179.812 ; gain = 656.664
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input   24 Bit       Adders := 1     
++---Registers : 
+	                6 Bit    Registers := 5     
+	                1 Bit    Registers := 1     
++---Muxes : 
+	   5 Input    3 Bit        Muxes := 1     
+	   2 Input    3 Bit        Muxes := 4     
+	   2 Input    2 Bit        Muxes := 3     
+	   3 Input    2 Bit        Muxes := 1     
+	   5 Input    1 Bit        Muxes := 1     
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 90 (col length:60)
+BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 1179.812 ; gain = 656.664
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1291.324 ; gain = 768.176
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1301.020 ; gain = 777.871
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1310.574 ; gain = 787.426
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 1517.348 ; gain = 994.199
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 1517.348 ; gain = 994.199
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 1517.348 ; gain = 994.199
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 1517.348 ; gain = 994.199
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 1517.348 ; gain = 994.199
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 1517.348 ; gain = 994.199
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |BUFG   |     1|
+|2     |CARRY4 |    10|
+|3     |LUT1   |     1|
+|4     |LUT2   |     1|
+|5     |LUT3   |    10|
+|6     |LUT5   |     1|
+|7     |LUT6   |     7|
+|8     |FDRE   |    53|
+|9     |IBUF   |    14|
+|10    |OBUF   |     2|
++------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 1517.348 ; gain = 994.199
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:33 ; elapsed = 00:00:44 . Memory (MB): peak = 1517.348 ; gain = 909.480
+Synthesis Optimization Complete : Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 1517.348 ; gain = 994.199
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1526.516 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1530.164 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: a782ca38
+INFO: [Common 17-83] Releasing license: Synthesis
+29 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:55 . Memory (MB): peak = 1530.164 ; gain = 1200.625
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1530.164 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1/digi_code.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file digi_code_utilization_synth.rpt -pb digi_code_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Tue Apr 29 11:02:00 2025...
diff --git a/tp5_n/tp5_n.runs/synth_1/digi_code_utilization_synth.pb b/tp5_n/tp5_n.runs/synth_1/digi_code_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..66374b2ddda4b8c35535083ba70be4a3e5719789
Binary files /dev/null and b/tp5_n/tp5_n.runs/synth_1/digi_code_utilization_synth.pb differ
diff --git a/tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.rpt b/tp5_n/tp5_n.runs/synth_1/digi_code_utilization_synth.rpt
similarity index 80%
rename from tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.rpt
rename to tp5_n/tp5_n.runs/synth_1/digi_code_utilization_synth.rpt
index c007b807dcb5149e8d83d9c16fb428577bf208dd..f3315c0889f2741f089945ce03e682a92a9c2ee1 100644
--- a/tp5_n/tp5_n.runs/synth_1/anti_rebond_utilization_synth.rpt
+++ b/tp5_n/tp5_n.runs/synth_1/digi_code_utilization_synth.rpt
@@ -1,13 +1,14 @@
-Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
-| Date         : Tue Apr 22 16:16:41 2025
-| Host         : b04p9 running 64-bit Ubuntu 22.04.5 LTS
-| Command      : report_utilization -file anti_rebond_utilization_synth.rpt -pb anti_rebond_utilization_synth.pb
-| Design       : anti_rebond
-| Device       : 7a35tcpg236-1
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 11:01:59 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_utilization -file digi_code_utilization_synth.rpt -pb digi_code_utilization_synth.pb
+| Design       : digi_code
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
 | Design State : Synthesized
------------------------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------
 
 Utilization Design Information
 
@@ -30,16 +31,18 @@ Table of Contents
 +-------------------------+------+-------+------------+-----------+-------+
 |        Site Type        | Used | Fixed | Prohibited | Available | Util% |
 +-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs*             |    3 |     0 |          0 |     20800 |  0.01 |
-|   LUT as Logic          |    3 |     0 |          0 |     20800 |  0.01 |
+| Slice LUTs*             |   19 |     0 |          0 |     20800 |  0.09 |
+|   LUT as Logic          |   19 |     0 |          0 |     20800 |  0.09 |
 |   LUT as Memory         |    0 |     0 |          0 |      9600 |  0.00 |
-| Slice Registers         |    7 |     0 |          0 |     41600 |  0.02 |
-|   Register as Flip Flop |    7 |     0 |          0 |     41600 |  0.02 |
+| Slice Registers         |   53 |     0 |          0 |     41600 |  0.13 |
+|   Register as Flip Flop |   53 |     0 |          0 |     41600 |  0.13 |
 |   Register as Latch     |    0 |     0 |          0 |     41600 |  0.00 |
 | F7 Muxes                |    0 |     0 |          0 |     16300 |  0.00 |
 | F8 Muxes                |    0 |     0 |          0 |      8150 |  0.00 |
 +-------------------------+------+-------+------------+-----------+-------+
 * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
 
 
 1.1 Summary of Registers by Type
@@ -57,7 +60,7 @@ Table of Contents
 | 0     |          Yes |           - |          Set |
 | 0     |          Yes |           - |        Reset |
 | 0     |          Yes |         Set |            - |
-| 7     |          Yes |       Reset |            - |
+| 53    |          Yes |       Reset |            - |
 +-------+--------------+-------------+--------------+
 
 
@@ -90,7 +93,7 @@ Table of Contents
 +-----------------------------+------+-------+------------+-----------+-------+
 |          Site Type          | Used | Fixed | Prohibited | Available | Util% |
 +-----------------------------+------+-------+------------+-----------+-------+
-| Bonded IOB                  |    4 |     0 |          0 |       106 |  3.77 |
+| Bonded IOB                  |   16 |     0 |          0 |       106 | 15.09 |
 | Bonded IPADs                |    0 |     0 |          0 |        10 |  0.00 |
 | Bonded OPADs                |    0 |     0 |          0 |         4 |  0.00 |
 | PHY_CONTROL                 |    0 |     0 |          0 |         5 |  0.00 |
@@ -149,10 +152,15 @@ Table of Contents
 +----------+------+---------------------+
 | Ref Name | Used | Functional Category |
 +----------+------+---------------------+
-| FDRE     |    7 |        Flop & Latch |
-| LUT3     |    4 |                 LUT |
-| IBUF     |    3 |                  IO |
-| OBUF     |    1 |                  IO |
+| FDRE     |   53 |        Flop & Latch |
+| IBUF     |   14 |                  IO |
+| LUT3     |   10 |                 LUT |
+| CARRY4   |   10 |          CarryLogic |
+| LUT6     |    7 |                 LUT |
+| OBUF     |    2 |                  IO |
+| LUT5     |    1 |                 LUT |
+| LUT2     |    1 |                 LUT |
+| LUT1     |    1 |                 LUT |
 | BUFG     |    1 |               Clock |
 +----------+------+---------------------+
 
diff --git a/tp5_n/tp5_n.runs/synth_1/gen_run.xml b/tp5_n/tp5_n.runs/synth_1/gen_run.xml
index 573f3605b21da31288aa28bd999b6830badbf67a..671279b57c22ed871810f8d55508bec14c31757a 100644
--- a/tp5_n/tp5_n.runs/synth_1/gen_run.xml
+++ b/tp5_n/tp5_n.runs/synth_1/gen_run.xml
@@ -1,14 +1,14 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1745331375">
-  <File Type="VDS-TIMING-PB" Name="anti_rebond_timing_summary_synth.pb"/>
-  <File Type="VDS-TIMINGSUMMARY" Name="anti_rebond_timing_summary_synth.rpt"/>
-  <File Type="RDS-DCP" Name="anti_rebond.dcp"/>
-  <File Type="RDS-UTIL-PB" Name="anti_rebond_utilization_synth.pb"/>
-  <File Type="RDS-UTIL" Name="anti_rebond_utilization_synth.rpt"/>
-  <File Type="RDS-PROPCONSTRS" Name="anti_rebond_drc_synth.rpt"/>
-  <File Type="RDS-RDS" Name="anti_rebond.vds"/>
-  <File Type="REPORTS-TCL" Name="anti_rebond_reports.tcl"/>
-  <File Type="PA-TCL" Name="anti_rebond.tcl"/>
+<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1745917256">
+  <File Type="PA-TCL" Name="digi_code.tcl"/>
+  <File Type="REPORTS-TCL" Name="digi_code_reports.tcl"/>
+  <File Type="RDS-RDS" Name="digi_code.vds"/>
+  <File Type="RDS-PROPCONSTRS" Name="digi_code_drc_synth.rpt"/>
+  <File Type="RDS-UTIL" Name="digi_code_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="digi_code_utilization_synth.pb"/>
+  <File Type="RDS-DCP" Name="digi_code.dcp"/>
+  <File Type="VDS-TIMINGSUMMARY" Name="digi_code_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="digi_code_timing_summary_synth.pb"/>
   <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
     <Filter Type="Srcs"/>
     <File Path="$PSRCDIR/sources_1/new/digi_code.vhd">
@@ -25,13 +25,7 @@
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PSRCDIR/sources_1/new/fpde.vhd">
-      <FileInfo>
-        <Attr Name="UsedIn" Val="synthesis"/>
-        <Attr Name="UsedIn" Val="simulation"/>
-      </FileInfo>
-    </File>
-    <File Path="$PSRCDIR/sources_1/new/fpd.vhd">
+    <File Path="$PSRCDIR/sources_1/new/Enable190.vhd">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
         <Attr Name="UsedIn" Val="simulation"/>
@@ -39,10 +33,10 @@
     </File>
     <Config>
       <Option Name="DesignMode" Val="RTL"/>
-      <Option Name="TopModule" Val="anti_rebond"/>
+      <Option Name="TopModule" Val="digi_code"/>
     </Config>
   </FileSet>
-  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
     <Filter Type="Constrs"/>
     <File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys3_Master.xdc">
       <FileInfo>
@@ -56,7 +50,7 @@
       <Option Name="ConstrsType" Val="XDC"/>
     </Config>
   </FileSet>
-  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
     <Filter Type="Utils"/>
     <Config>
       <Option Name="TopAutoSet" Val="TRUE"/>
diff --git a/tp5_n/tp5_n.runs/synth_1/htr.txt b/tp5_n/tp5_n.runs/synth_1/htr.txt
index b75ab37cc1d6b46874818fc4eab2b4fede846af4..f33abcb87e8e85853bc93bfddfb7cfd9fe3362d4 100644
--- a/tp5_n/tp5_n.runs/synth_1/htr.txt
+++ b/tp5_n/tp5_n.runs/synth_1/htr.txt
@@ -1,9 +1,10 @@
-#
-# Vivado(TM)
-# htr.txt: a Vivado-generated description of how-to-repeat the
-#          the basic steps of a run.  Note that runme.bat/sh needs
-#          to be invoked for Vivado to track run status.
-# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-#
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
 
-vivado -log anti_rebond.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source anti_rebond.tcl
+vivado -log digi_code.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source digi_code.tcl
diff --git a/tp5_n/tp5_n.runs/synth_1/vivado.jou b/tp5_n/tp5_n.runs/synth_1/vivado.jou
index f123e8a30e50bd0cc702e15ab3defebee543bf59..2b856a167c823d00197f892c0447a71abce5c31b 100644
--- a/tp5_n/tp5_n.runs/synth_1/vivado.jou
+++ b/tp5_n/tp5_n.runs/synth_1/vivado.jou
@@ -1,12 +1,24 @@
 #-----------------------------------------------------------
-# Vivado v2021.1 (64-bit)
-# SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
-# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
-# Start of session at: Tue Apr 22 16:16:17 2025
-# Process ID: 497770
-# Current directory: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1
-# Command line: vivado -log anti_rebond.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source anti_rebond.tcl
-# Log file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/anti_rebond.vds
-# Journal file: /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/vivado.jou
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Apr 29 11:01:00 2025
+# Process ID         : 7304
+# Current directory  : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1
+# Command line       : vivado.exe -log digi_code.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source digi_code.tcl
+# Log file           : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1/digi_code.vds
+# Journal file       : C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.runs/synth_1\vivado.jou
+# Running On         : LAPTOP-RU5MPQFG
+# Platform           : Windows Server 2016 or Windows 10
+# Operating System   : 26100
+# Processor Detail   : AMD Ryzen 5 5500U with Radeon Graphics         
+# CPU Frequency      : 2096 MHz
+# CPU Physical cores : 6
+# CPU Logical cores  : 12
+# Host memory        : 16468 MB
+# Swap memory        : 1073 MB
+# Total Virtual      : 17542 MB
+# Available Virtual  : 8688 MB
 #-----------------------------------------------------------
-source anti_rebond.tcl -notrace
+source digi_code.tcl -notrace
diff --git a/tp5_n/tp5_n.runs/synth_1/vivado.pb b/tp5_n/tp5_n.runs/synth_1/vivado.pb
index 514d904a788994349ef096c3c94834b12d88c129..fb9b82fc3bfa8f9028f85e99ed8c3ad832bb7c09 100644
Binary files a/tp5_n/tp5_n.runs/synth_1/vivado.pb and b/tp5_n/tp5_n.runs/synth_1/vivado.pb differ
diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/anti_rebond_vhdl.prj b/tp5_n/tp5_n.sim/sim_1/behav/xsim/anti_rebond_vhdl.prj
index 43a80cca854c85c7eaa9ca3b29ecd7a899d09679..70c7f5d16cfcff12a2bcebd2a3b2ee721dc1a66d 100644
--- a/tp5_n/tp5_n.sim/sim_1/behav/xsim/anti_rebond_vhdl.prj
+++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/anti_rebond_vhdl.prj
@@ -2,8 +2,7 @@
 vhdl xil_defaultlib  \
 "../../../../tp5_n.srcs/sources_1/new/digi_code.vhd" \
 "../../../../tp5_n.srcs/sources_1/new/anti_rebond.vhd" \
-"../../../../tp5_n.srcs/sources_1/new/fpde.vhd" \
-"../../../../tp5_n.srcs/sources_1/new/fpd.vhd" \
+"../../../../tp5_n.srcs/sources_1/new/Enable190.vhd" \
 
 # Do not sort compile order
 nosort
diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xelab.pb b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xelab.pb
index abf2a300e7c37c6b268968cc8bbd21a5f4bfb302..9bebbffba19eb66dc94d6afc7ac06712ff49f838 100644
Binary files a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xelab.pb and b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/Compile_Options.txt b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/Compile_Options.txt
index be1ef8782193b36edddb5ad67f8c0ae91c29034e..2aeb3797cfe13ac9d3927d0d0fdf9211e5c0b5b2 100644
--- a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/Compile_Options.txt
+++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/Compile_Options.txt
@@ -1 +1 @@
--wto "5e5d1ac8df47476c870b4cf306020630" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "anti_rebond_behav" "xil_defaultlib.anti_rebond" -log "elaborate.log" 
+--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "secureip" --snapshot "anti_rebond_behav" "xil_defaultlib.anti_rebond" -log "elaborate.log" 
diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/obj/xsim_1.c b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/obj/xsim_1.c
index eca938120fc222916f67277b61107546534045b1..d8469614abc4202d927393fefdd1a48a464d767f 100644
--- a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/obj/xsim_1.c
+++ b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/obj/xsim_1.c
@@ -65,8 +65,8 @@ const int NumRelocateId= 5;
 void relocate(char *dp)
 {
 	iki_relocate(dp, "xsim.dir/anti_rebond_behav/xsim.reloc",  (void **)funcTab, 5);
-	iki_vhdl_file_variable_register(dp + 2984);
-	iki_vhdl_file_variable_register(dp + 3040);
+	iki_vhdl_file_variable_register(dp + 3032);
+	iki_vhdl_file_variable_register(dp + 3088);
 
 
 	/*Populate the transaction function pointer field in the whole net structure */
@@ -101,6 +101,7 @@ extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
 int main(int argc, char **argv)
 {
     iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+    iki_set_xsimdir_location_if_remapped(argc, argv)  ;
     iki_set_sv_type_file_path_name("xsim.dir/anti_rebond_behav/xsim.svtype");
     iki_set_crvs_dump_file_path_name("xsim.dir/anti_rebond_behav/xsim.crvsdump");
     void* design_handle = iki_create_design("xsim.dir/anti_rebond_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/xsim.mem b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/xsim.mem
index e031b70fe39db3cefdc63a5b8edbd025601c1e28..06fff594689fc6a1e017827a7c60fd32aae8a641 100644
Binary files a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/xsim.mem and b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xsim.dir/anti_rebond_behav/xsim.mem differ
diff --git a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xvhdl.pb b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xvhdl.pb
index e4b98e59eb85bc5137030bb28f61eaaa600ac3bf..d4c1db7b417ba52f34552f2c429b65762afe3b71 100644
Binary files a/tp5_n/tp5_n.sim/sim_1/behav/xsim/xvhdl.pb and b/tp5_n/tp5_n.sim/sim_1/behav/xsim/xvhdl.pb differ
diff --git a/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd b/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd
index ba5070ffa02ba865dfc938c6e557b8a8fc4a5359..03acd113fbc190fd9c2fec2cd51d39fefb7c9ec3 100644
--- a/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd
+++ b/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd
@@ -76,7 +76,7 @@ begin
 
     clk_divide : clkdiv port map (
         clk => clk,
-        reset => open,
+        reset => '0',
         clk190 => clk190,
         E190 => E190
     );
@@ -89,30 +89,37 @@ begin
     );
     
     btn1_pulse : anti_rebond port map (
-        inp => btnL,
+        inp => btnD,
         E => E190,
         clk => clk,
         output => btnD_pulse
     );
  
      btn3_pulse : anti_rebond port map (
-        inp => btnL,
+        inp => btnU,
         E => E190,
         clk => clk,
         output => btnU_pulse
     );
 
      btn0_pulse : anti_rebond port map (
-        inp => btnL,
+        inp => btnR,
         E => E190,
         clk => clk,
         output => btnR_pulse
     );
+    
+    btnReset_pulse : anti_rebond port map (
+        inp => btnC,
+        E => E190,
+        clk => clk,
+        output => btnC_pulse
+    );
 
     SYNC_PROC : process(clk)
         begin
             if rising_edge(clk) then
-                if btnC = '1' then
+                if btnC_pulse = '1' then
                     state <= S0;
                 else
                     state <= next_state;
@@ -135,33 +142,25 @@ begin
         end process;
         
     -- Encodage du bouton appuyé
-    process(btnL, btnD, btnR, btnU)
-        variable pressed_count : integer := 0;
-    begin
-        pressed_count := 0;
-        if btnL = '1' then pressed_count := pressed_count + 1; end if;
-        if btnD = '1' then pressed_count := pressed_count + 1; end if;
-        if btnR = '1' then pressed_count := pressed_count + 1; end if;
-        if btnU = '1' then pressed_count := pressed_count + 1; end if;
-    
-        if pressed_count = 1 then
-            if btnL = '1' then
-                btn_value <= "10";
-            elsif btnD = '1' then
-                btn_value <= "01";
-            elsif btnR = '1' then
-                btn_value <= "00";
-            elsif btnU = '1' then
-                btn_value <= "11";
-            end if;
+    process(btnL_pulse, btnD_pulse, btnR_pulse, btnU_pulse)
+    begin    
+        if btnL_pulse = '1' then
+            btn_value <= "10";
+        elsif btnD_pulse = '1' then
+            btn_value <= "01";
+        elsif btnR_pulse = '1' then
+            btn_value <= "00";
+        elsif btnU_pulse = '1' then
+            btn_value <= "11";
         else
-            btn_value <= "ZZ"; -- ou une autre valeur spéciale pour indiquer un cas invalide
+            btn_value <= "--"; -- ou une autre valeur spéciale pour indiquer un cas invalide
         end if;
     end process;
     
     NEXT_STATE_DECODE : process(state, btn_value)
         begin
             next_state <= state; -- par défaut
+            
             case state is
                 when S0 =>
                     if btn_value = sw(1 downto 0) then
@@ -188,7 +187,7 @@ begin
                         next_state <= S0; -- Mauvaise touche : reset de la séquence
                     end if;    
                 when OPEND =>
-                    if btnC = '1' then
+                    if btnC_pulse = '1' then
                         next_state <= S0;
                     end if;
         
diff --git a/tp5_n/tp5_n.xpr b/tp5_n/tp5_n.xpr
index fcd5dd1f9653912bbf7879f8e0c182bcdf1a6a0b..bced36a83c37af906538b85c659cdac5879a8d7d 100644
--- a/tp5_n/tp5_n.xpr
+++ b/tp5_n/tp5_n.xpr
@@ -1,9 +1,10 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2021.1 (64-bit)              -->
-<!--                                                         -->
-<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.   -->
+<!-- Product Version: Vivado v2024.2 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Version="7" Minor="55" Path="/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.xpr">
+<Project Product="Vivado" Version="7" Minor="68" Path="C:/Users/mamad/INFO/hardware_design/tp5_n/tp5_n.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="5e5d1ac8df47476c870b4cf306020630"/>
@@ -12,21 +13,18 @@
     <Option Name="CompiledLibDirXSim" Val=""/>
     <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
     <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
-    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
     <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
     <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
     <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
     <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
     <Option Name="SimulatorInstallDirModelSim" Val=""/>
     <Option Name="SimulatorInstallDirQuesta" Val=""/>
-    <Option Name="SimulatorInstallDirIES" Val=""/>
     <Option Name="SimulatorInstallDirXcelium" Val=""/>
     <Option Name="SimulatorInstallDirVCS" Val=""/>
     <Option Name="SimulatorInstallDirRiviera" Val=""/>
     <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
     <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
     <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
-    <Option Name="SimulatorGccInstallDirIES" Val=""/>
     <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
@@ -34,7 +32,6 @@
     <Option Name="SimulatorVersionXsim" Val="2024.2"/>
     <Option Name="SimulatorVersionModelSim" Val="2024.1"/>
     <Option Name="SimulatorVersionQuesta" Val="2024.1"/>
-    <Option Name="SimulatorVersionIES" Val="15.20.083"/>
     <Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
     <Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
     <Option Name="SimulatorVersionRiviera" Val="2024.04"/>
@@ -42,7 +39,6 @@
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
     <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
-    <Option Name="SimulatorGccVersionIES" Val="6.2.0"/>
     <Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
     <Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
     <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
@@ -58,12 +54,14 @@
     <Option Name="IPCachePermission" Val="read"/>
     <Option Name="IPCachePermission" Val="write"/>
     <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
     <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="basys3"/>
-    <Option Name="WTXSimLaunchSim" Val="39"/>
+    <Option Name="WTXSimLaunchSim" Val="40"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -88,9 +86,10 @@
     <Option Name="SimTypes" Val="tlm_dpi"/>
     <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
     <Option Name="DcpsUptoDate" Val="TRUE"/>
-    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="UseInlineHdlIP" Val="TRUE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
   </Configuration>
-  <FileSets Version="1" Minor="31">
+  <FileSets Version="1" Minor="32">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
       <File Path="$PSRCDIR/sources_1/new/digi_code.vhd">
@@ -146,6 +145,9 @@
         <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
@@ -166,21 +168,15 @@
     <Simulator Name="Questa">
       <Option Name="Description" Val="Questa Advanced Simulator"/>
     </Simulator>
-    <Simulator Name="IES">
-      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
-    </Simulator>
-    <Simulator Name="Xcelium">
-      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
-    </Simulator>
-    <Simulator Name="VCS">
-      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
-    </Simulator>
     <Simulator Name="Riviera">
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="15">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PPRDIR/../C:/Users/mamad/INFO/hardware_design/tp5/tp5.srcs/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PPRDIR/../C:/Users/mamad/INFO/hardware_design/tp5/tp5.srcs/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
         <Step Id="synth_design"/>
@@ -190,7 +186,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../C:/Users/mamad/INFO/hardware_design/tp5/tp5.srcs/utils_1/imports/impl_1" LaunchOptions="-jobs 6 ">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../C:/Users/mamad/INFO/hardware_design/tp5/tp5.srcs/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
         <Step Id="init_design"/>
@@ -203,6 +199,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
diff --git a/tp_6/tp_6.cache/wt/webtalk_pa.xml b/tp_6/tp_6.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000000000000000000000000000000000000..f4f8ac2e2d87e05575c6248b130c3bd57d33f75b
--- /dev/null
+++ b/tp_6/tp_6.cache/wt/webtalk_pa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Tue Apr 29 12:04:57 2025">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="4bb21b1a01e241b788affb32a45261c8" type="ProjectID"/>
+<property name="ProjectIteration" value="4" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/tp_6/tp_6.hw/hw_1/hw.xml b/tp_6/tp_6.hw/hw_1/hw.xml
new file mode 100644
index 0000000000000000000000000000000000000000..d2a3e92a61652dbfe9c6c8c10451ba2903003c48
--- /dev/null
+++ b/tp_6/tp_6.hw/hw_1/hw.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.2 (64-bit)                                     -->
+<!--                                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                        -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.        -->
+
+<hwsession version="1" minor="2">
+  <device name="xc7a35t_0" gui_info=""/>
+  <ObjectList object_type="hw_device" gui_info="">
+    <Object name="xc7a35t_0" gui_info="">
+      <Properties Property="FULL_PROBES.FILE" value=""/>
+      <Properties Property="PROBES.FILE" value=""/>
+      <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/top_afficheur.bit"/>
+      <Properties Property="SLR.COUNT" value="1"/>
+    </Object>
+  </ObjectList>
+  <probeset name="hw project" active="false"/>
+</hwsession>
diff --git a/tp_6/tp_6.runs/.jobs/vrs_config_1.xml b/tp_6/tp_6.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b453e2861c904877973ed4690a17e51f630adcde
--- /dev/null
+++ b/tp_6/tp_6.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp_6/tp_6.runs/.jobs/vrs_config_2.xml b/tp_6/tp_6.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b453e2861c904877973ed4690a17e51f630adcde
--- /dev/null
+++ b/tp_6/tp_6.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp_6/tp_6.runs/.jobs/vrs_config_3.xml b/tp_6/tp_6.runs/.jobs/vrs_config_3.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b453e2861c904877973ed4690a17e51f630adcde
--- /dev/null
+++ b/tp_6/tp_6.runs/.jobs/vrs_config_3.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp_6/tp_6.runs/.jobs/vrs_config_4.xml b/tp_6/tp_6.runs/.jobs/vrs_config_4.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b453e2861c904877973ed4690a17e51f630adcde
--- /dev/null
+++ b/tp_6/tp_6.runs/.jobs/vrs_config_4.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Run Id="impl_1" LaunchDir="C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+		<Parent Id="synth_1"/>
+	</Run>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+	</Parameters>
+	<ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/tp_6/tp_6.runs/impl_1/clockInfo.txt b/tp_6/tp_6.runs/impl_1/clockInfo.txt
new file mode 100644
index 0000000000000000000000000000000000000000..b0d7278dba2627ea1822e9f56d41c13b0120a230
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/clockInfo.txt
@@ -0,0 +1,10 @@
+-------------------------------------
+| Tool Version : Vivado v.2024.2
+| Date         : Tue Apr 29 12:08:02 2025
+| Host         : LAPTOP-RU5MPQFG
+| Design       : design_1
+| Device       : xc7a35t-cpg236-1--
+-------------------------------------
+
+For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
+
diff --git a/tp_6/tp_6.runs/impl_1/gen_run.xml b/tp_6/tp_6.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..39a9d3d5bd8f9c8d097935737c72d8d0ef4d5ab3
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/gen_run.xml
@@ -0,0 +1,174 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1745921097">
+  <File Type="PA-TCL" Name="top_afficheur.tcl"/>
+  <File Type="REPORTS-TCL" Name="top_afficheur_reports.tcl"/>
+  <File Type="INIT-TIMING" Name="top_afficheur_timing_summary_init.rpt"/>
+  <File Type="OPT-DCP" Name="top_afficheur_opt.dcp"/>
+  <File Type="OPT-DRC" Name="top_afficheur_drc_opted.rpt"/>
+  <File Type="OPT-METHODOLOGY-DRC" Name="top_afficheur_methodology_drc_opted.rpt"/>
+  <File Type="OPT-HWDEF" Name="top_afficheur.hwdef"/>
+  <File Type="OPT-TIMING" Name="top_afficheur_timing_summary_opted.rpt"/>
+  <File Type="OPT-RQA-PB" Name="top_afficheur_rqa_opted.pb"/>
+  <File Type="PWROPT-DCP" Name="top_afficheur_pwropt.dcp"/>
+  <File Type="PWROPT-DRC" Name="top_afficheur_drc_pwropted.rpt"/>
+  <File Type="PWROPT-TIMING" Name="top_afficheur_timing_summary_pwropted.rpt"/>
+  <File Type="PLACE-DCP" Name="top_afficheur_placed.dcp"/>
+  <File Type="PLACE-IO" Name="top_afficheur_io_placed.rpt"/>
+  <File Type="PLACE-CLK" Name="top_afficheur_clock_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL" Name="top_afficheur_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL-PB" Name="top_afficheur_utilization_placed.pb"/>
+  <File Type="PLACE-CTRL" Name="top_afficheur_control_sets_placed.rpt"/>
+  <File Type="PLACE-SIMILARITY" Name="top_afficheur_incremental_reuse_placed.rpt"/>
+  <File Type="PLACE-PRE-SIMILARITY" Name="top_afficheur_incremental_reuse_pre_placed.rpt"/>
+  <File Type="PLACE-TIMING" Name="top_afficheur_timing_summary_placed.rpt"/>
+  <File Type="PLACE-RQA-PB" Name="top_afficheur_rqa_placed.pb"/>
+  <File Type="POSTPLACE-PWROPT-DCP" Name="top_afficheur_postplace_pwropt.dcp"/>
+  <File Type="POSTPLACE-PWROPT-TIMING" Name="top_afficheur_timing_summary_postplace_pwropted.rpt"/>
+  <File Type="PHYSOPT-DCP" Name="top_afficheur_physopt.dcp"/>
+  <File Type="PHYSOPT-DRC" Name="top_afficheur_drc_physopted.rpt"/>
+  <File Type="PHYSOPT-TIMING" Name="top_afficheur_timing_summary_physopted.rpt"/>
+  <File Type="ROUTE-ERROR-DCP" Name="top_afficheur_routed_error.dcp"/>
+  <File Type="ROUTE-DCP" Name="top_afficheur_routed.dcp"/>
+  <File Type="ROUTE-BLACKBOX-DCP" Name="top_afficheur_routed_bb.dcp"/>
+  <File Type="ROUTE-DRC" Name="top_afficheur_drc_routed.rpt"/>
+  <File Type="ROUTE-DRC-PB" Name="top_afficheur_drc_routed.pb"/>
+  <File Type="ROUTE-DRC-RPX" Name="top_afficheur_drc_routed.rpx"/>
+  <File Type="ROUTE-METHODOLOGY-DRC" Name="top_afficheur_methodology_drc_routed.rpt"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="top_afficheur_methodology_drc_routed.rpx"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="top_afficheur_methodology_drc_routed.pb"/>
+  <File Type="ROUTE-PWR" Name="top_afficheur_power_routed.rpt"/>
+  <File Type="ROUTE-PWR-SUM" Name="top_afficheur_power_summary_routed.pb"/>
+  <File Type="ROUTE-PWR-RPX" Name="top_afficheur_power_routed.rpx"/>
+  <File Type="ROUTE-STATUS" Name="top_afficheur_route_status.rpt"/>
+  <File Type="ROUTE-STATUS-PB" Name="top_afficheur_route_status.pb"/>
+  <File Type="ROUTE-TIMINGSUMMARY" Name="top_afficheur_timing_summary_routed.rpt"/>
+  <File Type="ROUTE-TIMING-PB" Name="top_afficheur_timing_summary_routed.pb"/>
+  <File Type="ROUTE-TIMING-RPX" Name="top_afficheur_timing_summary_routed.rpx"/>
+  <File Type="ROUTE-SIMILARITY" Name="top_afficheur_incremental_reuse_routed.rpt"/>
+  <File Type="ROUTE-CLK" Name="top_afficheur_clock_utilization_routed.rpt"/>
+  <File Type="ROUTE-BUS-SKEW" Name="top_afficheur_bus_skew_routed.rpt"/>
+  <File Type="ROUTE-BUS-SKEW-PB" Name="top_afficheur_bus_skew_routed.pb"/>
+  <File Type="ROUTE-BUS-SKEW-RPX" Name="top_afficheur_bus_skew_routed.rpx"/>
+  <File Type="ROUTE-RQS-PB" Name="top_afficheur_rqs_routed.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-DCP" Name="top_afficheur_postroute_physopt.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="top_afficheur_postroute_physopt_bb.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="top_afficheur_timing_summary_postroute_physopted.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="top_afficheur_timing_summary_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="top_afficheur_timing_summary_postroute_physopted.rpx"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="top_afficheur_bus_skew_postroute_physopted.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="top_afficheur_bus_skew_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="top_afficheur_bus_skew_postroute_physopted.rpx"/>
+  <File Type="BG-BIT" Name="top_afficheur.bit"/>
+  <File Type="BG-BIN" Name="top_afficheur.bin"/>
+  <File Type="BITSTR-MSK" Name="top_afficheur.msk"/>
+  <File Type="BITSTR-RBT" Name="top_afficheur.rbt"/>
+  <File Type="BITSTR-NKY" Name="top_afficheur.nky"/>
+  <File Type="BITSTR-BMM" Name="top_afficheur_bd.bmm"/>
+  <File Type="BITSTR-MMI" Name="top_afficheur.mmi"/>
+  <File Type="PDI-FILE" Name="top_afficheur.pdi"/>
+  <File Type="BOOT-PDI-FILE" Name="top_afficheur_boot.pdi"/>
+  <File Type="PL-PDI-FILE" Name="top_afficheur_pld.pdi"/>
+  <File Type="RCFI_FILE" Name="top_afficheur.rcfi"/>
+  <File Type="CFI_FILE" Name="top_afficheur.cfi"/>
+  <File Type="RNPI_FILE" Name="top_afficheur.rnpi"/>
+  <File Type="NPI_FILE" Name="top_afficheur.npi"/>
+  <File Type="RBD_FILE" Name="top_afficheur.rbd"/>
+  <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+  <File Type="BITSTR-LTX" Name="top_afficheur.ltx"/>
+  <File Type="BITSTR-SYSDEF" Name="top_afficheur.sysdef"/>
+  <File Type="BG-BGN" Name="top_afficheur.bgn"/>
+  <File Type="BG-DRC" Name="top_afficheur.drc"/>
+  <File Type="RDI-RDI" Name="top_afficheur.vdi"/>
+  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+  <File Type="ROUTE-RQS" Name="top_afficheur_routed.rqs"/>
+  <File Type="POSTROUTE-PHYSOPT-RQS" Name="top_afficheur_postroute_physopted.rqs"/>
+  <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PSRCDIR/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd"/>
+        <Attr Name="ImportTime" Val="1745867194"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/new/afficheur_16.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd"/>
+        <Attr Name="ImportTime" Val="1744632998"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/new/top_afficheur.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd">
+      <FileInfo>
+        <Attr Name="AutoDisabled" Val="1"/>
+        <Attr Name="ImportPath" Val="$PPRDIR/../tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd"/>
+        <Attr Name="ImportTime" Val="1745865959"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="top_afficheur"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys3_Master.xdc">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc"/>
+        <Attr Name="ImportTime" Val="1745865959"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+    <Filter Type="Utils"/>
+    <File Path="$PSRCDIR/utils_1/imports/synth_1/top_afficheur.dcp">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedInSteps" Val="synth_1"/>
+        <Attr Name="AutoDcp" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+      <Desc>Default settings for Implementation.</Desc>
+    </StratHandle>
+    <Step Id="init_design"/>
+    <Step Id="opt_design"/>
+    <Step Id="power_opt_design"/>
+    <Step Id="place_design"/>
+    <Step Id="post_place_power_opt_design"/>
+    <Step Id="phys_opt_design"/>
+    <Step Id="route_design"/>
+    <Step Id="post_route_phys_opt_design"/>
+    <Step Id="write_bitstream"/>
+  </Strategy>
+</GenRun>
diff --git a/tp_6/tp_6.runs/impl_1/htr.txt b/tp_6/tp_6.runs/impl_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2be969e601a3bd7f9481745514f2a057f97b27cb
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/htr.txt
@@ -0,0 +1,10 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+
+vivado -log top_afficheur.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_afficheur.tcl -notrace
diff --git a/tp_6/tp_6.runs/impl_1/init_design.pb b/tp_6/tp_6.runs/impl_1/init_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3528b91c5b9c93bfa83a3f83a106c5add536b4d2
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/init_design.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/opt_design.pb b/tp_6/tp_6.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..df599e081088a4bb16d34e8a766635be1f9926a5
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/opt_design.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/phys_opt_design.pb b/tp_6/tp_6.runs/impl_1/phys_opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..48397410d02b8cb67433a6a84e9b7eeee8ff10f2
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/phys_opt_design.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/place_design.pb b/tp_6/tp_6.runs/impl_1/place_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..c160607bac45b6633c4c75d2bc27d97533c26f07
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/place_design.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/route_design.pb b/tp_6/tp_6.runs/impl_1/route_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..802b535b9786800ea11678d9ccfe5fdf1ea55402
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/route_design.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur.tcl b/tp_6/tp_6.runs/impl_1/top_afficheur.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8ccda817fc281804442c83cece5784e12ed1d92d
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur.tcl
@@ -0,0 +1,312 @@
+namespace eval ::optrace {
+  variable script "C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1/top_afficheur.tcl"
+  variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+  namespace eval ::dispatch {
+    variable connected false
+    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+      set result "true"
+      if {[catch {
+        if {[lsearch -exact [package names] DispatchTcl] < 0} {
+          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
+        }
+        if {$result eq "false"} {
+          puts "WARNING: Could not load dispatch client library"
+        }
+        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+        if { $connect_id eq "" } {
+          puts "WARNING: Could not initialize dispatch client"
+        } else {
+          puts "INFO: Dispatch client connection id - $connect_id"
+          set connected true
+        }
+      } catch_res]} {
+        puts "WARNING: failed to connect to dispatch server - $catch_res"
+      }
+    }
+  }
+}
+if {$::dispatch::connected} {
+  # Remove the dummy proc if it exists.
+  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+    rename ::OPTRACE ""
+  }
+  proc ::OPTRACE { task action {tags {} } } {
+    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+  }
+  # dispatch is generic. We specifically want to attach logging.
+  ::vitis_log::connect_client
+} else {
+  # Add dummy proc if it doesn't exist.
+  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+        # Do nothing
+    }
+  }
+}
+
+proc start_step { step } {
+  set stopFile ".stop.rst"
+  if {[file isfile .stop.rst]} {
+    puts ""
+    puts "*** Halting run - EA reset detected ***"
+    puts ""
+    puts ""
+    return -code error
+  }
+  set beginFile ".$step.begin.rst"
+  set platform "$::tcl_platform(platform)"
+  set user "$::tcl_platform(user)"
+  set pid [pid]
+  set host ""
+  if { [string equal $platform unix] } {
+    if { [info exist ::env(HOSTNAME)] } {
+      set host $::env(HOSTNAME)
+    } elseif { [info exist ::env(HOST)] } {
+      set host $::env(HOST)
+    }
+  } else {
+    if { [info exist ::env(COMPUTERNAME)] } {
+      set host $::env(COMPUTERNAME)
+    }
+  }
+  set ch [open $beginFile w]
+  puts $ch "<?xml version=\"1.0\"?>"
+  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+  puts $ch "    </Process>"
+  puts $ch "</ProcessHandle>"
+  close $ch
+}
+
+proc end_step { step } {
+  set endFile ".$step.end.rst"
+  set ch [open $endFile w]
+  close $ch
+}
+
+proc step_failed { step } {
+  set endFile ".$step.error.rst"
+  set ch [open $endFile w]
+  close $ch
+OPTRACE "impl_1" END { }
+}
+
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+  create_msg_db init_design.pb
+  set_param chipscope.maxJobs 3
+  set_param xicom.use_bs_reader 1
+  set_param runs.launchOptions { -jobs 6  }
+OPTRACE "create in-memory project" START { }
+  create_project -in_memory -part xc7a35tcpg236-1
+  set_property board_part_repo_paths {C:/Users/mamad/AppData/Roaming/Xilinx/Vivado/2024.2/xhub/board_store/xilinx_board_store} [current_project]
+  set_property board_part digilentinc.com:basys3:part0:1.2 [current_project]
+  set_property design_mode GateLvl [current_fileset]
+  set_param project.singleFileAddWarning.threshold 0
+OPTRACE "create in-memory project" END { }
+OPTRACE "set parameters" START { }
+  set_property webtalk.parent_dir C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.cache/wt [current_project]
+  set_property parent.project_path C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.xpr [current_project]
+  set_property ip_output_repo C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.cache/ip [current_project]
+  set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "set parameters" END { }
+OPTRACE "add files" START { }
+  add_files -quiet C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1/top_afficheur.dcp
+OPTRACE "read constraints: implementation" START { }
+  read_xdc C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc
+OPTRACE "read constraints: implementation" END { }
+OPTRACE "read constraints: implementation_pre" START { }
+OPTRACE "read constraints: implementation_pre" END { }
+OPTRACE "add files" END { }
+OPTRACE "link_design" START { }
+  link_design -top top_afficheur -part xc7a35tcpg236-1 
+OPTRACE "link_design" END { }
+OPTRACE "gray box cells" START { }
+OPTRACE "gray box cells" END { }
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+OPTRACE "init_design_write_hwdef" END { }
+  close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+  step_failed init_design
+  return -code error $RESULT
+} else {
+  end_step init_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+  create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+  opt_design 
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "opt_design reports" START { REPORT }
+  set_param project.isImplRun true
+  generate_parallel_reports -reports { "report_drc -file top_afficheur_drc_opted.rpt -pb top_afficheur_drc_opted.pb -rpx top_afficheur_drc_opted.rpx"  }
+  set_param project.isImplRun false
+OPTRACE "opt_design reports" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force top_afficheur_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+  close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+  step_failed opt_design
+  return -code error $RESULT
+} else {
+  end_step opt_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+  create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+  if { [llength [get_debug_cores -quiet] ] > 0 }  { 
+OPTRACE "implement_debug_core" START { }
+    implement_debug_core 
+OPTRACE "implement_debug_core" END { }
+  } 
+OPTRACE "place_design" START { }
+  place_design 
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "place_design reports" START { REPORT }
+  set_param project.isImplRun true
+  generate_parallel_reports -reports { "report_io -file top_afficheur_io_placed.rpt" "report_utilization -file top_afficheur_utilization_placed.rpt -pb top_afficheur_utilization_placed.pb" "report_control_sets -verbose -file top_afficheur_control_sets_placed.rpt"  }
+  set_param project.isImplRun false
+OPTRACE "place_design reports" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force top_afficheur_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+  close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+  step_failed place_design
+  return -code error $RESULT
+} else {
+  end_step place_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
+start_step phys_opt_design
+set ACTIVE_STEP phys_opt_design
+set rc [catch {
+  create_msg_db phys_opt_design.pb
+OPTRACE "read constraints: phys_opt_design" START { }
+OPTRACE "read constraints: phys_opt_design" END { }
+OPTRACE "phys_opt_design" START { }
+  phys_opt_design 
+OPTRACE "phys_opt_design" END { }
+OPTRACE "read constraints: phys_opt_design_post" START { }
+OPTRACE "read constraints: phys_opt_design_post" END { }
+OPTRACE "phys_opt_design report" START { REPORT }
+OPTRACE "phys_opt_design report" END { }
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force top_afficheur_physopt.dcp
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
+  close_msg_db -file phys_opt_design.pb
+} RESULT]
+if {$rc} {
+  step_failed phys_opt_design
+  return -code error $RESULT
+} else {
+  end_step phys_opt_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Physical Opt Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+  create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+  route_design 
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "route_design reports" START { REPORT }
+  set_param project.isImplRun true
+  generate_parallel_reports -reports { "report_drc -file top_afficheur_drc_routed.rpt -pb top_afficheur_drc_routed.pb -rpx top_afficheur_drc_routed.rpx" "report_methodology -file top_afficheur_methodology_drc_routed.rpt -pb top_afficheur_methodology_drc_routed.pb -rpx top_afficheur_methodology_drc_routed.rpx" "report_power -file top_afficheur_power_routed.rpt -pb top_afficheur_power_summary_routed.pb -rpx top_afficheur_power_routed.rpx" "report_route_status -file top_afficheur_route_status.rpt -pb top_afficheur_route_status.pb" "report_timing_summary -max_paths 10 -report_unconstrained -file top_afficheur_timing_summary_routed.rpt -pb top_afficheur_timing_summary_routed.pb -rpx top_afficheur_timing_summary_routed.rpx -warn_on_violation " "report_incremental_reuse -file top_afficheur_incremental_reuse_routed.rpt" "report_clock_utilization -file top_afficheur_clock_utilization_routed.rpt" "report_bus_skew -warn_on_violation -file top_afficheur_bus_skew_routed.rpt -pb top_afficheur_bus_skew_routed.pb -rpx top_afficheur_bus_skew_routed.rpx"  }
+  set_param project.isImplRun false
+OPTRACE "route_design reports" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force top_afficheur_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design misc" START { }
+  close_msg_db -file route_design.pb
+} RESULT]
+if {$rc} {
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+  write_checkpoint -force top_afficheur_routed_error.dcp
+  step_failed route_design
+  return -code error $RESULT
+} else {
+  end_step route_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+  create_msg_db write_bitstream.pb
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+  catch { write_mem_info -force -no_partial_mmi top_afficheur.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+  write_bitstream -force top_afficheur.bit 
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+  catch {write_debug_probes -quiet -force top_afficheur}
+  catch {file copy -force top_afficheur.ltx debug_nets.ltx}
+  close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+  step_failed write_bitstream
+  return -code error $RESULT
+} else {
+  end_step write_bitstream
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur.vdi b/tp_6/tp_6.runs/impl_1/top_afficheur.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..9288da027da7426b778819db934a09d81b255913
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur.vdi
@@ -0,0 +1,673 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Apr 29 12:06:52 2025
+# Process ID         : 4340
+# Current directory  : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1
+# Command line       : vivado.exe -log top_afficheur.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top_afficheur.tcl -notrace
+# Log file           : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1/top_afficheur.vdi
+# Journal file       : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1\vivado.jou
+# Running On         : LAPTOP-RU5MPQFG
+# Platform           : Windows Server 2016 or Windows 10
+# Operating System   : 26100
+# Processor Detail   : AMD Ryzen 5 5500U with Radeon Graphics         
+# CPU Frequency      : 2096 MHz
+# CPU Physical cores : 6
+# CPU Logical cores  : 12
+# Host memory        : 16468 MB
+# Swap memory        : 1073 MB
+# Total Virtual      : 17542 MB
+# Available Virtual  : 8620 MB
+#-----------------------------------------------------------
+source top_afficheur.tcl -notrace
+Command: link_design -top top_afficheur -part xc7a35tcpg236-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 534.902 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'dp'. [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:100]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:100]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'dp'. [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:101]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:101]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 670.137 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+7 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 674.137 ; gain = 344.883
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 714.586 ; gain = 40.449
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 2b9b00fcd
+
+Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1229.734 ; gain = 515.148
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 2b9b00fcd
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2b9b00fcd
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 1 Initialization | Checksum: 2b9b00fcd
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 2b9b00fcd
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 2b9b00fcd
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 2 Timer Update And Timing Data Collection | Checksum: 2b9b00fcd
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 3 Retarget
+INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 2b9b00fcd
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Retarget | Checksum: 2b9b00fcd
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 2b9b00fcd
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Constant propagation | Checksum: 2b9b00fcd
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
+Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 5 Sweep | Checksum: 2b74d5d39
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Sweep | Checksum: 2b74d5d39
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 2b74d5d39
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.155 . Memory (MB): peak = 1634.379 ; gain = 0.000
+BUFG optimization | Checksum: 2b74d5d39
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 2b74d5d39
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.158 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Shift Register Optimization | Checksum: 2b74d5d39
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 2b74d5d39
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.161 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Post Processing Netlist | Checksum: 2b74d5d39
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 234404cce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.171 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 234404cce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.192 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 9 Finalization | Checksum: 234404cce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.193 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               0  |                                              0  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 234404cce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.197 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 234404cce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 234404cce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Ending Netlist Obfuscation Task | Checksum: 234404cce
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1634.379 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+27 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1634.379 ; gain = 960.242
+INFO: [Vivado 12-24828] Executing command : report_drc -file top_afficheur_drc_opted.rpt -pb top_afficheur_drc_opted.pb -rpx top_afficheur_drc_opted.rpx
+Command: report_drc -file top_afficheur_drc_opted.rpt -pb top_afficheur_drc_opted.pb -rpx top_afficheur_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2024.2/data/ip'.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1/top_afficheur_drc_opted.rpt.
+report_drc completed successfully
+report_drc: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1634.379 ; gain = 0.000
+generate_parallel_reports: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1634.379 ; gain = 0.000
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.084 . Memory (MB): peak = 1634.379 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1/top_afficheur_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1851c4856
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1331b7a58
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.489 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 1.3 Build Placer Netlist Model
+WARNING: [Place 30-2953] Timing driven mode will be turned off because no critical terminals were found.
+Phase 1.3 Build Placer Netlist Model | Checksum: 1a3b82509
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.771 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1a3b82509
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.777 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 1 Placer Initialization | Checksum: 1a3b82509
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.781 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1a3b82509
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.785 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1a3b82509
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.787 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 1a3b82509
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.788 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 2.4 Global Place Phase1
+Phase 2.4 Global Place Phase1 | Checksum: 22ef679a5
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 2.5 Global Place Phase2
+WARNING: [Place 46-29] Timing had been disabled during Placer and, therefore, physical synthesis in Placer will be skipped.
+Phase 2.5 Global Place Phase2 | Checksum: 1a58712d6
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 2 Global Placement | Checksum: 1a58712d6
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 1a58712d6
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1cee637b8
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 140460db1
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 140460db1
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1fa3c910f
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 1fa3c910f
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 1fa3c910f
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 3 Detail Placement | Checksum: 1fa3c910f
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+Phase 4.1 Post Commit Optimization | Checksum: 1fa3c910f
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1fa3c910f
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1fa3c910f
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 4.3 Placer Reporting | Checksum: 1fa3c910f
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1634.379 ; gain = 0.000
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f9352727
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Ending Placer Task | Checksum: 17b50f0d0
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1634.379 ; gain = 0.000
+46 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 1634.379 ; gain = 0.000
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 2 threads.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file top_afficheur_utilization_placed.rpt -pb top_afficheur_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_afficheur_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1634.379 ; gain = 0.000
+INFO: [Vivado 12-24828] Executing command : report_io -file top_afficheur_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1634.379 ; gain = 0.000
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1634.379 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.100 . Memory (MB): peak = 1634.379 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1/top_afficheur_placed.dcp' has been generated.
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+
+Starting Initial Update Timing Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1643.605 ; gain = 9.227
+INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 7.715 | TNS= 0.000 | 
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+58 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1661.488 ; gain = 0.020
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1661.488 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1661.488 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1661.488 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1661.488 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1661.488 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.101 . Memory (MB): peak = 1661.488 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1/top_afficheur_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 6df98273 ConstDB: 0 ShapeSum: 6cd61206 RouteDB: a0815c57
+Post Restoration Checksum: NetGraph: ecdabea7 | NumContArr: f7c205e8 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 369eeb9c9
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:50 . Memory (MB): peak = 1757.273 ; gain = 95.785
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 369eeb9c9
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:50 . Memory (MB): peak = 1757.273 ; gain = 95.785
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 369eeb9c9
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:50 . Memory (MB): peak = 1757.273 ; gain = 95.785
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 21854e1b4
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:51 . Memory (MB): peak = 1767.938 ; gain = 106.449
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.621  | TNS=0.000  | WHS=0.006  | THS=0.000  |
+
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.000398629 %
+  Global Horizontal Routing Utilization  = 0.00741801 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 57
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 56
+  Number of Partially Routed Nets     = 1
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: 2907d5ab1
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 2907d5ab1
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: fbeb3c52
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+Phase 4 Initial Routing | Checksum: fbeb3c52
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.337  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 5.1 Global Iteration 0 | Checksum: 2ae9f240a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+Phase 5 Rip-up And Reroute | Checksum: 2ae9f240a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 2ae9f240a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 2ae9f240a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+Phase 6 Delay and Skew Optimization | Checksum: 2ae9f240a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.430  | TNS=0.000  | WHS=0.309  | THS=0.000  |
+
+Phase 7.1 Hold Fix Iter | Checksum: 1f6e4d63a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+Phase 7 Post Hold Fix | Checksum: 1f6e4d63a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:51 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.0304552 %
+  Global Horizontal Routing Utilization  = 0.0607756 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 8 Route finalize | Checksum: 1f6e4d63a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:52 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 1f6e4d63a
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:52 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 2441f9085
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:52 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 2441f9085
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:52 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=7.430  | TNS=0.000  | WHS=0.309  | THS=0.000  |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 2441f9085
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:52 . Memory (MB): peak = 1774.234 ; gain = 112.746
+Total Elapsed time in route_design: 51.544 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 1b4a307ce
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:52 . Memory (MB): peak = 1774.234 ; gain = 112.746
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 1b4a307ce
+
+Time (s): cpu = 00:00:53 ; elapsed = 00:00:52 . Memory (MB): peak = 1774.234 ; gain = 112.746
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+69 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:53 ; elapsed = 00:00:52 . Memory (MB): peak = 1774.234 ; gain = 112.746
+INFO: [Vivado 12-24828] Executing command : report_drc -file top_afficheur_drc_routed.rpt -pb top_afficheur_drc_routed.pb -rpx top_afficheur_drc_routed.rpx
+Command: report_drc -file top_afficheur_drc_routed.rpt -pb top_afficheur_drc_routed.pb -rpx top_afficheur_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1/top_afficheur_drc_routed.rpt.
+report_drc completed successfully
+report_drc: Time (s): cpu = 00:00:14 ; elapsed = 00:00:08 . Memory (MB): peak = 1819.859 ; gain = 45.625
+INFO: [Vivado 12-24828] Executing command : report_methodology -file top_afficheur_methodology_drc_routed.rpt -pb top_afficheur_methodology_drc_routed.pb -rpx top_afficheur_methodology_drc_routed.rpx
+Command: report_methodology -file top_afficheur_methodology_drc_routed.rpt -pb top_afficheur_methodology_drc_routed.pb -rpx top_afficheur_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 2 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1/top_afficheur_methodology_drc_routed.rpt.
+report_methodology completed successfully
+report_drc: Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 1839.227 ; gain = 19.367
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_afficheur_timing_summary_routed.rpt -pb top_afficheur_timing_summary_routed.pb -rpx top_afficheur_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 2 threads.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file top_afficheur_route_status.rpt -pb top_afficheur_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_afficheur_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_power -file top_afficheur_power_routed.rpt -pb top_afficheur_power_summary_routed.pb -rpx top_afficheur_power_routed.rpx
+Command: report_power -file top_afficheur_power_routed.rpt -pb top_afficheur_power_summary_routed.pb -rpx top_afficheur_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+86 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_afficheur_clock_utilization_routed.rpt
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_afficheur_bus_skew_routed.rpt -pb top_afficheur_bus_skew_routed.pb -rpx top_afficheur_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
+generate_parallel_reports: Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 1846.125 ; gain = 71.891
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1846.125 ; gain = 0.000
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1846.125 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1846.125 ; gain = 0.000
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1846.125 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1846.125 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1846.125 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.118 . Memory (MB): peak = 1846.125 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1/top_afficheur_routed.dcp' has been generated.
+Command: write_bitstream -force top_afficheur.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado 12-3199] DRC finished with 0 Errors
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./top_afficheur.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
+INFO: [Common 17-83] Releasing license: Implementation
+101 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2309.344 ; gain = 463.219
+INFO: [Common 17-206] Exiting Vivado at Tue Apr 29 12:09:43 2025...
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_bus_skew_routed.pb b/tp_6/tp_6.runs/impl_1/top_afficheur_bus_skew_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_bus_skew_routed.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_bus_skew_routed.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_bus_skew_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..9223f13e653af8d69d4dd6c2d9bc399f5ecd2d3f
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_bus_skew_routed.rpt
@@ -0,0 +1,16 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 12:09:14 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_bus_skew -warn_on_violation -file top_afficheur_bus_skew_routed.rpt -pb top_afficheur_bus_skew_routed.pb -rpx top_afficheur_bus_skew_routed.rpx
+| Design       : top_afficheur
+| Device       : 7a35t-cpg236
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_clock_utilization_routed.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_clock_utilization_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..793137e58b1a36f50914a6cad766e94615389caf
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_clock_utilization_routed.rpt
@@ -0,0 +1,160 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 12:09:14 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_clock_utilization -file top_afficheur_clock_utilization_routed.rpt
+| Design       : top_afficheur
+| Device       : 7a35t-cpg236
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Local Clock Details
+5. Clock Regions: Key Resource Utilization
+6. Clock Regions : Global Clock Summary
+7. Device Cell Placement Summary for Global Clock g0
+8. Clock Region Cell Placement per Global Clock: Region X0Y0
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type     | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL |    1 |        32 |   0 |            0 |      0 |
+| BUFH     |    0 |        72 |   0 |            0 |      0 |
+| BUFIO    |    0 |        20 |   0 |            0 |      0 |
+| BUFMR    |    0 |        10 |   0 |            0 |      0 |
+| BUFR     |    0 |        20 |   0 |            0 |      0 |
+| MMCM     |    0 |         5 |   0 |            0 |      0 |
+| PLL      |    0 |         5 |   0 |            0 |      0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site          | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock       | Driver Pin           | Net           |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
+| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y0 | n/a          |                 1 |          19 |               0 |       10.000 | sys_clk_pin | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site      | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin      | Net      |
++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
+| src0      | g0        | IBUF/O          | IOB_X1Y26  | IOB_X1Y26 | X1Y0         |           1 |               0 |              10.000 | sys_clk_pin  | clk_IBUF_inst/O | clk_IBUF |
++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+4. Local Clock Details
+----------------------
+
++----------+-----------------+------------+-----------------+--------------+-------------+-----------------+--------------+-------+----------------------+-----------------+
+| Local Id | Driver Type/Pin | Constraint | Site/BEL        | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin           | Net             |
++----------+-----------------+------------+-----------------+--------------+-------------+-----------------+--------------+-------+----------------------+-----------------+
+| 0        | FDCE/Q          | None       | SLICE_X0Y22/CFF | X0Y0         |           6 |               1 |              |       | clkdiv_i/q_reg[18]/Q | clkdiv_i/out[0] |
++----------+-----------------+------------+-----------------+--------------+-------------+-----------------+--------------+-------+----------------------+-----------------+
+* Local Clocks in this context represents only clocks driven by non-global buffers
+** Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+*** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+5. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   19 |  1200 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    6 |  1500 |    0 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
+| X0Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1200 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1500 |    0 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
+| X0Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1800 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X1Y2              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |   950 |    0 |   300 |    0 |    10 |    0 |     5 |    0 |    20 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+6. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+|    | X0 | X1 |
++----+----+----+
+| Y2 |  0 |  0 |
+| Y1 |  0 |  0 |
+| Y0 |  0 |  0 |
++----+----+----+
+
+
+7. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock       | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net           |
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
+| g0        | BUFG/O          | n/a               | sys_clk_pin |      10.000 | {0.000 5.000} |          19 |        0 |              0 |        0 | clk_IBUF_BUFG |
++-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+-----+----+-----------------------+
+|    | X0  | X1 | HORIZONTAL PROG DELAY |
++----+-----+----+-----------------------+
+| Y2 |   0 |  0 |                     - |
+| Y1 |   0 |  0 |                     - |
+| Y0 |  19 |  0 |                     0 |
++----+-----+----+-----------------------+
+
+
+8. Clock Region Cell Placement per Global Clock: Region X0Y0
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net           |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
+| g0        | n/a   | BUFG/O          | None       |          19 |               0 | 19 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | clk_IBUF_BUFG |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives 
+set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]
+
+# Location of IO Primitives which is load of clock spine
+
+# Location of clock ports
+set_property LOC IOB_X1Y26 [get_ports clk]
+
+# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
+#startgroup
+create_pblock {CLKAG_clk_IBUF_BUFG}
+add_cells_to_pblock [get_pblocks  {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
+resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}
+#endgroup
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_control_sets_placed.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_control_sets_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..00bf7bae5ccb84842767709748ba38af6a75df2d
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_control_sets_placed.rpt
@@ -0,0 +1,80 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 12:08:04 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_control_sets -verbose -file top_afficheur_control_sets_placed.rpt
+| Design       : top_afficheur
+| Device       : xc7a35t
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+|                          Status                          | Count |
++----------------------------------------------------------+-------+
+| Total control sets                                       |     2 |
+|    Minimum number of control sets                        |     2 |
+|    Addition due to synthesis replication                 |     0 |
+|    Addition due to physical synthesis replication        |     0 |
+| Unused register locations in slices containing registers |     7 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+|       Fanout       | Count |
++--------------------+-------+
+| Total control sets |     2 |
+| >= 0 to < 4        |     0 |
+| >= 4 to < 6        |     0 |
+| >= 6 to < 8        |     1 |
+| >= 8 to < 10       |     0 |
+| >= 10 to < 12      |     0 |
+| >= 12 to < 14      |     0 |
+| >= 14 to < 16      |     0 |
+| >= 16              |     1 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No           | No                    | No                     |               6 |            1 |
+| No           | No                    | Yes                    |              19 |            5 |
+| No           | Yes                   | No                     |               0 |            0 |
+| Yes          | No                    | No                     |               0 |            0 |
+| Yes          | No                    | Yes                    |               0 |            0 |
+| Yes          | Yes                   | No                     |               0 |            0 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++------------------+---------------+------------------+------------------+----------------+--------------+
+|   Clock Signal   | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++------------------+---------------+------------------+------------------+----------------+--------------+
+|  clkdiv_i/out[0] |               |                  |                1 |              6 |         6.00 |
+|  clk_IBUF_BUFG   |               | reset_IBUF       |                5 |             19 |         3.80 |
++------------------+---------------+------------------+------------------+----------------+--------------+
+
+
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_drc_opted.pb b/tp_6/tp_6.runs/impl_1/top_afficheur_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_drc_opted.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_drc_opted.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_drc_opted.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..21c78d3345a099f6c2009279426a5d6887b0cd52
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_drc_opted.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 12:07:54 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_drc -file top_afficheur_drc_opted.rpt -pb top_afficheur_drc_opted.pb -rpx top_afficheur_drc_opted.rpx
+| Design       : top_afficheur
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max checks: <unlimited>
+             Checks found: 1
++----------+----------+-----------------------------------------------------+--------+
+| Rule     | Severity | Description                                         | Checks |
++----------+----------+-----------------------------------------------------+--------+
+| CFGBVS-1 | Warning  | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1      |
++----------+----------+-----------------------------------------------------+--------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_drc_routed.pb b/tp_6/tp_6.runs/impl_1/top_afficheur_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_drc_routed.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_drc_routed.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..49bff097fd045085d27cdff070f65042715a8a57
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_drc_routed.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 12:09:06 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_drc -file top_afficheur_drc_routed.rpt -pb top_afficheur_drc_routed.pb -rpx top_afficheur_drc_routed.rpx
+| Design       : top_afficheur
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max checks: <unlimited>
+             Checks found: 1
++----------+----------+-----------------------------------------------------+--------+
+| Rule     | Severity | Description                                         | Checks |
++----------+----------+-----------------------------------------------------+--------+
+| CFGBVS-1 | Warning  | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1      |
++----------+----------+-----------------------------------------------------+--------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_io_placed.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_io_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..7539730a2b19deebec2edad023266796b7ff72e4
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_io_placed.rpt
@@ -0,0 +1,280 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version              : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date                      : Tue Apr 29 12:08:04 2025
+| Host                      : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command                   : report_io -file top_afficheur_io_placed.rpt
+| Design                    : top_afficheur
+| Device                    : xc7a35t
+| Speed File                : -1
+| Package                   : cpg236
+| Package Version           : FINAL 2014-02-19
+| Package Pin Delay Version : VERS. 2.0 2014-02-19
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+|            29 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type  | Pin Name                     | Use           | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A2         |             |            | MGTPTXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A4         |             |            | MGTPRXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A6         |             |            | MGTPRXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A8         |             |            | MGTREFCLK0N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A10        |             |            | MGTREFCLK1N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A11        |             | Dedicated  | DXP_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A12        |             | Dedicated  | VP_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A13        |             | Dedicated  | VREFN_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A14        |             | High Range | IO_L6P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A15        |             | High Range | IO_L6N_T0_VREF_16            | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A16        |             | High Range | IO_L12P_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A17        |             | High Range | IO_L12N_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A18        |             | High Range | IO_L19N_T3_VREF_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B1         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B2         |             |            | MGTPTXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B4         |             |            | MGTPRXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B6         |             |            | MGTPRXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B8         |             |            | MGTREFCLK0P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B10        |             |            | MGTREFCLK1P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B11        |             | Dedicated  | DXN_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B12        |             | Dedicated  | VREFP_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B13        |             | Dedicated  | VN_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B14        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B15        |             | High Range | IO_L11N_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B16        |             | High Range | IO_L13N_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B17        |             | High Range | IO_L14N_T2_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B18        |             | High Range | IO_L19P_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B19        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| C1         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C4         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C5         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C6         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C7         |             |            | MGTRREF_216                  | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C8         |             | Dedicated  | TCK_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C9         |             | Dedicated  | VCCBATT_0                    | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C10        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C11        |             | Dedicated  | CCLK_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C12        |             | Dedicated  | GNDADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C13        |             | Dedicated  | VCCADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C14        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| C15        |             | High Range | IO_L11P_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C16        |             | High Range | IO_L13P_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C17        |             | High Range | IO_L14P_T2_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C18        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| C19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D1         |             |            | MGTPTXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D2         |             |            | MGTPTXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D17        |             | High Range | IO_0_14                      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D18        |             | High Range | IO_L1P_T0_D00_MOSI_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D19        |             | High Range | IO_L1N_T0_D01_DIN_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E1         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E2         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E17        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E18        |             | High Range | IO_L3P_T0_DQS_PUDC_B_14      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E19        |             | High Range | IO_L3N_T0_DQS_EMCCLK_14      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F3         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F17        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| F18        |             | High Range | IO_L2N_T0_D03_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G2         |             | High Range | IO_L1N_T0_AD4N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G3         |             | High Range | IO_L1P_T0_AD4P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G7         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G9         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G12        |             | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| G13        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| G17        |             | High Range | IO_L5N_T0_D07_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G18        |             | High Range | IO_L2P_T0_D02_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G19        |             | High Range | IO_L4N_T0_D05_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H1         |             | High Range | IO_L3P_T0_DQS_AD5P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H2         |             | High Range | IO_L2P_T0_AD12P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H3         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| H7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H9         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H13        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| H17        |             | High Range | IO_L5P_T0_D06_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H18        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H19        |             | High Range | IO_L4P_T0_D04_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J1         |             | High Range | IO_L3N_T0_DQS_AD5N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J2         |             | High Range | IO_L2N_T0_AD12N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J3         |             | High Range | IO_L7P_T1_AD6P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| J8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J13        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| J17        |             | High Range | IO_L7P_T1_D09_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J18        |             | High Range | IO_L7N_T1_D10_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J19        |             | High Range | IO_L6N_T0_D08_VREF_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K1         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| K2         |             | High Range | IO_L5P_T0_AD13P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K3         |             | High Range | IO_L7N_T1_AD6N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| K8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K12        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| K13        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| K17        |             | High Range | IO_L12N_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K18        |             | High Range | IO_L8N_T1_D12_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K19        |             | High Range | IO_L6P_T0_FCS_B_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L1         |             | High Range | IO_L6N_T0_VREF_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L2         |             | High Range | IO_L5N_T0_AD13N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L3         |             | High Range | IO_L8P_T1_AD14P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| L8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L12        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| L13        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| L17        |             | High Range | IO_L12P_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L18        |             | High Range | IO_L8P_T1_D11_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M1         |             | High Range | IO_L9N_T1_DQS_AD7N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M2         |             | High Range | IO_L9P_T1_DQS_AD7P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M3         |             | High Range | IO_L8N_T1_AD14N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| M8         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| M9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M11        |             |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M12        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| M13        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M17        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| M18        |             | High Range | IO_L11P_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M19        |             | High Range | IO_L11N_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N1         |             | High Range | IO_L10N_T1_AD15N_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N2         |             | High Range | IO_L10P_T1_AD15P_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N3         |             | High Range | IO_L12P_T1_MRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N7         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| N8         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| N9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N11        |             |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N13        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N17        |             | High Range | IO_L13P_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N18        |             | High Range | IO_L9P_T1_DQS_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N19        |             | High Range | IO_L9N_T1_DQS_D13_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P1         |             | High Range | IO_L19N_T3_VREF_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P3         |             | High Range | IO_L12N_T1_MRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P17        |             | High Range | IO_L13N_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P18        |             | High Range | IO_L14P_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P19        |             | High Range | IO_L10P_T1_D14_14            | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R1         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| R2         | sw[15]      | High Range | IO_L1P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| R3         | sw[11]      | High Range | IO_L2P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| R17        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| R18        |             | High Range | IO_L14N_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R19        |             | High Range | IO_L10N_T1_D15_14            | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T1         | sw[14]      | High Range | IO_L3P_T0_DQS_34             | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| T2         | sw[10]      | High Range | IO_L1N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| T3         | sw[9]       | High Range | IO_L2N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| T17        |             | High Range | IO_L17P_T2_A14_D30_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T18        |             | High Range | IO_L17N_T2_A13_D29_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U1         | sw[13]      | High Range | IO_L3N_T0_DQS_34             | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| U2         | an[0]       | High Range | IO_L9N_T1_DQS_34             | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| U3         |             | High Range | IO_L9P_T1_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U4         | an[1]       | High Range | IO_L11P_T1_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| U5         | seg[4]      | High Range | IO_L16P_T2_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| U6         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U7         | seg[6]      | High Range | IO_L19P_T3_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| U8         | seg[2]      | High Range | IO_L14P_T2_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| U9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U10        |             | Dedicated  | M2_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U11        |             | Dedicated  | INIT_B_0                     | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U12        |             | Dedicated  | DONE_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U13        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| U14        |             | High Range | IO_25_14                     | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U15        |             | High Range | IO_L23P_T3_A03_D19_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U16        |             | High Range | IO_L23N_T3_A02_D18_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U17        |             | High Range | IO_L18P_T2_A12_D28_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U18        | reset       | High Range | IO_L18N_T2_A11_D27_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| U19        |             | High Range | IO_L15P_T2_DQS_RDWR_B_14     | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V1         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| V2         | sw[8]       | High Range | IO_L5P_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| V3         |             | High Range | IO_L6P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V4         | an[2]       | High Range | IO_L11N_T1_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| V5         | seg[5]      | High Range | IO_L16N_T2_34                | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| V6         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| V7         |             | High Range | IO_L19N_T3_VREF_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V8         | seg[3]      | High Range | IO_L14N_T2_SRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| V9         |             | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| V10        |             | Dedicated  | PROGRAM_B_0                  | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V11        |             | Dedicated  | CFGBVS_0                     | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V12        |             | Dedicated  | M0_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V13        |             | High Range | IO_L24P_T3_A01_D17_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V14        |             | High Range | IO_L24N_T3_A00_D16_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V15        | sw[5]       | High Range | IO_L21P_T3_DQS_14            | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| V16        | sw[1]       | High Range | IO_L19P_T3_A10_D26_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| V17        | sw[0]       | High Range | IO_L19N_T3_A09_D25_VREF_14   | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| V18        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| V19        |             | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| W2         | sw[12]      | High Range | IO_L5N_T0_34                 | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W3         |             | High Range | IO_L6N_T0_VREF_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W4         | an[3]       | High Range | IO_L12N_T1_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W5         | clk         | High Range | IO_L12P_T1_MRCC_34           | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W6         | seg[1]      | High Range | IO_L13N_T2_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W7         | seg[0]      | High Range | IO_L13P_T2_MRCC_34           | OUTPUT        | LVCMOS33    |      34 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W8         |             | Dedicated  | TDO_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W9         |             | Dedicated  | TMS_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W10        |             | Dedicated  | TDI_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W11        |             | Dedicated  | M1_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| W13        | sw[7]       | High Range | IO_L22P_T3_A05_D21_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W14        | sw[6]       | High Range | IO_L22N_T3_A04_D20_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W15        | sw[4]       | High Range | IO_L21N_T3_DQS_A06_D22_14    | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W16        | sw[2]       | High Range | IO_L20P_T3_A08_D24_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W17        | sw[3]       | High Range | IO_L20N_T3_A07_D23_14        | INPUT         | LVCMOS33    |      14 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| W18        |             | High Range | IO_L16P_T2_CSI_B_14          | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W19        |             | High Range | IO_L16N_T2_A15_D31_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_methodology_drc_routed.pb b/tp_6/tp_6.runs/impl_1/top_afficheur_methodology_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..92272e8a8791eb5ba1109513cf1532eb88e7125e
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_methodology_drc_routed.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_methodology_drc_routed.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_methodology_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..3cfded8889212f72a36bb0b63dfee43ec870b538
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_methodology_drc_routed.rpt
@@ -0,0 +1,71 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 12:09:13 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_methodology -file top_afficheur_methodology_drc_routed.rpt -pb top_afficheur_methodology_drc_routed.pb -rpx top_afficheur_methodology_drc_routed.rpx
+| Design       : top_afficheur
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Fully Routed
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+             Max checks: <unlimited>
+             Checks found: 7
++-----------+------------------+-------------------------------+--------+
+| Rule      | Severity         | Description                   | Checks |
++-----------+------------------+-------------------------------+--------+
+| TIMING-17 | Critical Warning | Non-clocked sequential cell   | 6      |
+| TIMING-18 | Warning          | Missing input or output delay | 1      |
++-----------+------------------+-------------------------------+--------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-17#1 Critical Warning
+Non-clocked sequential cell  
+The clock pin afficheur/FSM_sequential_state_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#2 Critical Warning
+Non-clocked sequential cell  
+The clock pin afficheur/FSM_sequential_state_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#3 Critical Warning
+Non-clocked sequential cell  
+The clock pin afficheur/an_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#4 Critical Warning
+Non-clocked sequential cell  
+The clock pin afficheur/an_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#5 Critical Warning
+Non-clocked sequential cell  
+The clock pin afficheur/an_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#6 Critical Warning
+Non-clocked sequential cell  
+The clock pin afficheur/an_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-18#1 Warning
+Missing input or output delay  
+An input delay is missing on reset relative to the rising and/or falling clock edge(s) of sys_clk_pin.
+Related violations: <none>
+
+
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_opt.dcp b/tp_6/tp_6.runs/impl_1/top_afficheur_opt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..467bcd8523bdad4497c03fd59dd0ad0f49d96028
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_opt.dcp differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_physopt.dcp b/tp_6/tp_6.runs/impl_1/top_afficheur_physopt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..158cd5ae5a21ceec2409a4f97dcdd2e1f254638f
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_physopt.dcp differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_placed.dcp b/tp_6/tp_6.runs/impl_1/top_afficheur_placed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..e3138ba0578fb4424ee5169c46ffc95321b8a3df
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_placed.dcp differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_power_routed.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_power_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..e048505651e837d662f210d00585497cb5f0ff00
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_power_routed.rpt
@@ -0,0 +1,146 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version     : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date             : Tue Apr 29 12:09:14 2025
+| Host             : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command          : report_power -file top_afficheur_power_routed.rpt -pb top_afficheur_power_summary_routed.pb -rpx top_afficheur_power_routed.rpx
+| Design           : top_afficheur
+| Device           : xc7a35tcpg236-1
+| Design State     : routed
+| Grade            : commercial
+| Process          : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W)  | 0.102        |
+| Design Power Budget (W)  | Unspecified* |
+| Power Budget Margin (W)  | NA           |
+| Dynamic (W)              | 0.030        |
+| Device Static (W)        | 0.072        |
+| Effective TJA (C/W)      | 5.0          |
+| Max Ambient (C)          | 84.5         |
+| Junction Temperature (C) | 25.5         |
+| Confidence Level         | Low          |
+| Setting File             | ---          |
+| Simulation Activity File | ---          |
+| Design Nets Matched      | NA           |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Clocks         |    <0.001 |        3 |       --- |             --- |
+| Slice Logic    |    <0.001 |       52 |       --- |             --- |
+|   LUT as Logic |    <0.001 |       12 |     20800 |            0.06 |
+|   Register     |    <0.001 |       25 |     41600 |            0.06 |
+|   CARRY4       |    <0.001 |        5 |      8150 |            0.06 |
+|   Others       |     0.000 |        4 |       --- |             --- |
+| Signals        |    <0.001 |       57 |       --- |             --- |
+| I/O            |     0.029 |       29 |       106 |           27.36 |
+| Static Power   |     0.072 |          |           |                 |
+| Total          |     0.102 |          |           |                 |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint    |       1.000 |     0.011 |       0.001 |      0.010 |       NA    | Unspecified | NA         |
+| Vccaux    |       1.800 |     0.014 |       0.001 |      0.013 |       NA    | Unspecified | NA         |
+| Vcco33    |       3.300 |     0.009 |       0.008 |      0.001 |       NA    | Unspecified | NA         |
+| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+| User Input Data             | Confidence | Details                                                | Action                                                                                                             |
++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High       | Design is routed                                       |                                                                                                                    |
+| Clock nodes activity        | Medium     | More than 5% of clocks are missing user specification  | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
+| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
+| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views         |
+| Device models               | High       | Device models are Production                           |                                                                                                                    |
+|                             |            |                                                        |                                                                                                                    |
+| Overall confidence level    | Low        |                                                        |                                                                                                                    |
++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C)      | 25.0                     |
+| ThetaJA (C/W)         | 5.0                      |
+| Airflow (LFM)         | 250                      |
+| Heat Sink             | medium (Medium Profile)  |
+| ThetaSA (C/W)         | 4.6                      |
+| Board Selection       | medium (10"x10")         |
+| # of Board Layers     | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0                     |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++-------------+--------+-----------------+
+| Clock       | Domain | Constraint (ns) |
++-------------+--------+-----------------+
+| sys_clk_pin | clk    |            10.0 |
++-------------+--------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++---------------+-----------+
+| Name          | Power (W) |
++---------------+-----------+
+| top_afficheur |     0.030 |
++---------------+-----------+
+
+
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_power_summary_routed.pb b/tp_6/tp_6.runs/impl_1/top_afficheur_power_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..79883aa976eeeaf7cfc842e15428a609b038b05a
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_power_summary_routed.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_route_status.pb b/tp_6/tp_6.runs/impl_1/top_afficheur_route_status.pb
new file mode 100644
index 0000000000000000000000000000000000000000..c1bfa81aeedeff7dbf3718b6ab52f93777c934e8
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_route_status.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_route_status.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_route_status.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..6a93f5d84f7a71d4ca95482e1589079b05d34ae9
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_route_status.rpt
@@ -0,0 +1,11 @@
+Design Route Status
+                                               :      # nets :
+   ------------------------------------------- : ----------- :
+   # of logical nets.......................... :         116 :
+       # of nets not needing routing.......... :          55 :
+           # of internally routed nets........ :          55 :
+       # of routable nets..................... :          61 :
+           # of fully routed nets............. :          61 :
+       # of nets with routing errors.......... :           0 :
+   ------------------------------------------- : ----------- :
+
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_routed.dcp b/tp_6/tp_6.runs/impl_1/top_afficheur_routed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..a4e45d768682b97fdcb8429e624c4342b1814e4a
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_routed.dcp differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_timing_summary_routed.pb b/tp_6/tp_6.runs/impl_1/top_afficheur_timing_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..0873ec5784c5a3b11f0114efc014b3d256b16827
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_timing_summary_routed.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_timing_summary_routed.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_timing_summary_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..4b620a2406fdc36ae0af83487483e3d2a017fba0
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_timing_summary_routed.rpt
@@ -0,0 +1,2655 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 12:09:13 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_timing_summary -max_paths 10 -report_unconstrained -file top_afficheur_timing_summary_routed.rpt -pb top_afficheur_timing_summary_routed.pb -rpx top_afficheur_timing_summary_routed.rpx -warn_on_violation
+| Design       : top_afficheur
+| Device       : 7a35t-cpg236
+| Speed File   : -1  PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+  Enable Multi Corner Analysis               :  Yes
+  Enable Pessimism Removal                   :  Yes
+  Pessimism Removal Resolution               :  Nearest Common Node
+  Enable Input Delay Default Clock           :  No
+  Enable Preset / Clear Arcs                 :  No
+  Disable Flight Delays                      :  No
+  Ignore I/O Paths                           :  No
+  Timing Early Launch at Borrowing Latches   :  No
+  Borrow Time for Max Delay Exceptions       :  Yes
+  Merge Timing Exceptions                    :  Yes
+  Inter-SLR Compensation                     :  Conservative
+
+  Corner  Analyze    Analyze    
+  Name    Max Paths  Min Paths  
+  ------  ---------  ---------  
+  Slow    Yes        Yes        
+  Fast    Yes        Yes        
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule       Severity          Description                    Violations  
+---------  ----------------  -----------------------------  ----------  
+TIMING-17  Critical Warning  Non-clocked sequential cell    6           
+TIMING-18  Warning           Missing input or output delay  1           
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (6)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (6)
+5. checking no_input_delay (1)
+6. checking no_output_delay (11)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (6)
+------------------------
+ There are 6 register/latch pins with no clock driven by root clock pin: clkdiv_i/q_reg[18]/Q (HIGH)
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (6)
+------------------------------------------------
+ There are 6 pins that are not constrained for maximum delay. (HIGH)
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (1)
+------------------------------
+ There is 1 input port with no input delay specified. (HIGH)
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (11)
+--------------------------------
+ There are 11 ports with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+      7.431        0.000                      0                   19        0.324        0.000                      0                   19        4.500        0.000                       0                    20  
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock        Waveform(ns)       Period(ns)      Frequency(MHz)
+-----        ------------       ----------      --------------
+sys_clk_pin  {0.000 5.000}      10.000          100.000         
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+sys_clk_pin         7.431        0.000                      0                   19        0.324        0.000                      0                   19        4.500        0.000                       0                    20  
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+
+
+------------------------------------------------------------------------------------------------
+| User Ignored Path Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock    
+----------    ----------    --------    
+
+
+------------------------------------------------------------------------------------------------
+| Unconstrained Path Table
+| ------------------------
+------------------------------------------------------------------------------------------------
+
+Path Group    From Clock    To Clock    
+----------    ----------    --------    
+(none)                                    
+(none)                      sys_clk_pin   
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  sys_clk_pin
+  To Clock:  sys_clk_pin
+
+Setup :            0  Failing Endpoints,  Worst Slack        7.431ns,  Total Violation        0.000ns
+Hold  :            0  Failing Endpoints,  Worst Slack        0.324ns,  Total Violation        0.000ns
+PW    :            0  Failing Endpoints,  Worst Slack        4.500ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             7.431ns  (required time - arrival time)
+  Source:                 clkdiv_i/q_reg[1]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[17]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.568ns  (logic 1.806ns (70.331%)  route 0.762ns (29.669%))
+  Logic Levels:           5  (CARRY4=5)
+  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.846ns = ( 14.846 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.148ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.627     5.148    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.456     5.604 r  clkdiv_i/q_reg[1]/Q
+                         net (fo=1, routed)           0.762     6.366    clkdiv_i/q_reg_n_0_[1]
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     7.040 r  clkdiv_i/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.040    clkdiv_i/q_reg[0]_i_1_n_0
+    SLICE_X0Y19          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.154 r  clkdiv_i/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.154    clkdiv_i/q_reg[4]_i_1_n_0
+    SLICE_X0Y20          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.268 r  clkdiv_i/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.268    clkdiv_i/q_reg[8]_i_1_n_0
+    SLICE_X0Y21          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.382 r  clkdiv_i/q_reg[12]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.382    clkdiv_i/q_reg[12]_i_1_n_0
+    SLICE_X0Y22          CARRY4 (Prop_carry4_CI_O[1])
+                                                      0.334     7.716 r  clkdiv_i/q_reg[16]_i_1/O[1]
+                         net (fo=1, routed)           0.000     7.716    clkdiv_i/q_reg[16]_i_1_n_6
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[17]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.505    14.846    clkdiv_i/clk
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[17]/C
+                         clock pessimism              0.274    15.120    
+                         clock uncertainty           -0.035    15.085    
+    SLICE_X0Y22          FDCE (Setup_fdce_C_D)        0.062    15.147    clkdiv_i/q_reg[17]
+  -------------------------------------------------------------------
+                         required time                         15.147    
+                         arrival time                          -7.716    
+  -------------------------------------------------------------------
+                         slack                                  7.431    
+
+Slack (MET) :             7.526ns  (required time - arrival time)
+  Source:                 clkdiv_i/q_reg[1]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[18]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.473ns  (logic 1.711ns (69.191%)  route 0.762ns (30.809%))
+  Logic Levels:           5  (CARRY4=5)
+  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.846ns = ( 14.846 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.148ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.627     5.148    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.456     5.604 r  clkdiv_i/q_reg[1]/Q
+                         net (fo=1, routed)           0.762     6.366    clkdiv_i/q_reg_n_0_[1]
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     7.040 r  clkdiv_i/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.040    clkdiv_i/q_reg[0]_i_1_n_0
+    SLICE_X0Y19          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.154 r  clkdiv_i/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.154    clkdiv_i/q_reg[4]_i_1_n_0
+    SLICE_X0Y20          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.268 r  clkdiv_i/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.268    clkdiv_i/q_reg[8]_i_1_n_0
+    SLICE_X0Y21          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.382 r  clkdiv_i/q_reg[12]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.382    clkdiv_i/q_reg[12]_i_1_n_0
+    SLICE_X0Y22          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.621 r  clkdiv_i/q_reg[16]_i_1/O[2]
+                         net (fo=1, routed)           0.000     7.621    clkdiv_i/q_reg[16]_i_1_n_5
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[18]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.505    14.846    clkdiv_i/clk
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[18]/C
+                         clock pessimism              0.274    15.120    
+                         clock uncertainty           -0.035    15.085    
+    SLICE_X0Y22          FDCE (Setup_fdce_C_D)        0.062    15.147    clkdiv_i/q_reg[18]
+  -------------------------------------------------------------------
+                         required time                         15.147    
+                         arrival time                          -7.621    
+  -------------------------------------------------------------------
+                         slack                                  7.526    
+
+Slack (MET) :             7.542ns  (required time - arrival time)
+  Source:                 clkdiv_i/q_reg[1]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[16]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.457ns  (logic 1.695ns (68.990%)  route 0.762ns (31.010%))
+  Logic Levels:           5  (CARRY4=5)
+  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.846ns = ( 14.846 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.148ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.627     5.148    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.456     5.604 r  clkdiv_i/q_reg[1]/Q
+                         net (fo=1, routed)           0.762     6.366    clkdiv_i/q_reg_n_0_[1]
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     7.040 r  clkdiv_i/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.040    clkdiv_i/q_reg[0]_i_1_n_0
+    SLICE_X0Y19          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.154 r  clkdiv_i/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.154    clkdiv_i/q_reg[4]_i_1_n_0
+    SLICE_X0Y20          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.268 r  clkdiv_i/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.268    clkdiv_i/q_reg[8]_i_1_n_0
+    SLICE_X0Y21          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.382 r  clkdiv_i/q_reg[12]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.382    clkdiv_i/q_reg[12]_i_1_n_0
+    SLICE_X0Y22          CARRY4 (Prop_carry4_CI_O[0])
+                                                      0.223     7.605 r  clkdiv_i/q_reg[16]_i_1/O[0]
+                         net (fo=1, routed)           0.000     7.605    clkdiv_i/q_reg[16]_i_1_n_7
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[16]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.505    14.846    clkdiv_i/clk
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[16]/C
+                         clock pessimism              0.274    15.120    
+                         clock uncertainty           -0.035    15.085    
+    SLICE_X0Y22          FDCE (Setup_fdce_C_D)        0.062    15.147    clkdiv_i/q_reg[16]
+  -------------------------------------------------------------------
+                         required time                         15.147    
+                         arrival time                          -7.605    
+  -------------------------------------------------------------------
+                         slack                                  7.542    
+
+Slack (MET) :             7.547ns  (required time - arrival time)
+  Source:                 clkdiv_i/q_reg[1]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[13]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.454ns  (logic 1.692ns (68.952%)  route 0.762ns (31.048%))
+  Logic Levels:           4  (CARRY4=4)
+  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.848ns = ( 14.848 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.148ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.627     5.148    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.456     5.604 r  clkdiv_i/q_reg[1]/Q
+                         net (fo=1, routed)           0.762     6.366    clkdiv_i/q_reg_n_0_[1]
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     7.040 r  clkdiv_i/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.040    clkdiv_i/q_reg[0]_i_1_n_0
+    SLICE_X0Y19          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.154 r  clkdiv_i/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.154    clkdiv_i/q_reg[4]_i_1_n_0
+    SLICE_X0Y20          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.268 r  clkdiv_i/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.268    clkdiv_i/q_reg[8]_i_1_n_0
+    SLICE_X0Y21          CARRY4 (Prop_carry4_CI_O[1])
+                                                      0.334     7.602 r  clkdiv_i/q_reg[12]_i_1/O[1]
+                         net (fo=1, routed)           0.000     7.602    clkdiv_i/q_reg[12]_i_1_n_6
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[13]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.507    14.848    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[13]/C
+                         clock pessimism              0.274    15.122    
+                         clock uncertainty           -0.035    15.087    
+    SLICE_X0Y21          FDCE (Setup_fdce_C_D)        0.062    15.149    clkdiv_i/q_reg[13]
+  -------------------------------------------------------------------
+                         required time                         15.149    
+                         arrival time                          -7.602    
+  -------------------------------------------------------------------
+                         slack                                  7.547    
+
+Slack (MET) :             7.568ns  (required time - arrival time)
+  Source:                 clkdiv_i/q_reg[1]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[15]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.433ns  (logic 1.671ns (68.684%)  route 0.762ns (31.316%))
+  Logic Levels:           4  (CARRY4=4)
+  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.848ns = ( 14.848 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.148ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.627     5.148    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.456     5.604 r  clkdiv_i/q_reg[1]/Q
+                         net (fo=1, routed)           0.762     6.366    clkdiv_i/q_reg_n_0_[1]
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     7.040 r  clkdiv_i/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.040    clkdiv_i/q_reg[0]_i_1_n_0
+    SLICE_X0Y19          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.154 r  clkdiv_i/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.154    clkdiv_i/q_reg[4]_i_1_n_0
+    SLICE_X0Y20          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.268 r  clkdiv_i/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.268    clkdiv_i/q_reg[8]_i_1_n_0
+    SLICE_X0Y21          CARRY4 (Prop_carry4_CI_O[3])
+                                                      0.313     7.581 r  clkdiv_i/q_reg[12]_i_1/O[3]
+                         net (fo=1, routed)           0.000     7.581    clkdiv_i/q_reg[12]_i_1_n_4
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[15]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.507    14.848    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[15]/C
+                         clock pessimism              0.274    15.122    
+                         clock uncertainty           -0.035    15.087    
+    SLICE_X0Y21          FDCE (Setup_fdce_C_D)        0.062    15.149    clkdiv_i/q_reg[15]
+  -------------------------------------------------------------------
+                         required time                         15.149    
+                         arrival time                          -7.581    
+  -------------------------------------------------------------------
+                         slack                                  7.568    
+
+Slack (MET) :             7.642ns  (required time - arrival time)
+  Source:                 clkdiv_i/q_reg[1]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[14]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.359ns  (logic 1.597ns (67.702%)  route 0.762ns (32.298%))
+  Logic Levels:           4  (CARRY4=4)
+  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.848ns = ( 14.848 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.148ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.627     5.148    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.456     5.604 r  clkdiv_i/q_reg[1]/Q
+                         net (fo=1, routed)           0.762     6.366    clkdiv_i/q_reg_n_0_[1]
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     7.040 r  clkdiv_i/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.040    clkdiv_i/q_reg[0]_i_1_n_0
+    SLICE_X0Y19          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.154 r  clkdiv_i/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.154    clkdiv_i/q_reg[4]_i_1_n_0
+    SLICE_X0Y20          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.268 r  clkdiv_i/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.268    clkdiv_i/q_reg[8]_i_1_n_0
+    SLICE_X0Y21          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.507 r  clkdiv_i/q_reg[12]_i_1/O[2]
+                         net (fo=1, routed)           0.000     7.507    clkdiv_i/q_reg[12]_i_1_n_5
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[14]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.507    14.848    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[14]/C
+                         clock pessimism              0.274    15.122    
+                         clock uncertainty           -0.035    15.087    
+    SLICE_X0Y21          FDCE (Setup_fdce_C_D)        0.062    15.149    clkdiv_i/q_reg[14]
+  -------------------------------------------------------------------
+                         required time                         15.149    
+                         arrival time                          -7.507    
+  -------------------------------------------------------------------
+                         slack                                  7.642    
+
+Slack (MET) :             7.658ns  (required time - arrival time)
+  Source:                 clkdiv_i/q_reg[1]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[12]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.343ns  (logic 1.581ns (67.481%)  route 0.762ns (32.519%))
+  Logic Levels:           4  (CARRY4=4)
+  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.848ns = ( 14.848 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.148ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.627     5.148    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.456     5.604 r  clkdiv_i/q_reg[1]/Q
+                         net (fo=1, routed)           0.762     6.366    clkdiv_i/q_reg_n_0_[1]
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     7.040 r  clkdiv_i/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.040    clkdiv_i/q_reg[0]_i_1_n_0
+    SLICE_X0Y19          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.154 r  clkdiv_i/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.154    clkdiv_i/q_reg[4]_i_1_n_0
+    SLICE_X0Y20          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.268 r  clkdiv_i/q_reg[8]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.268    clkdiv_i/q_reg[8]_i_1_n_0
+    SLICE_X0Y21          CARRY4 (Prop_carry4_CI_O[0])
+                                                      0.223     7.491 r  clkdiv_i/q_reg[12]_i_1/O[0]
+                         net (fo=1, routed)           0.000     7.491    clkdiv_i/q_reg[12]_i_1_n_7
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[12]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.507    14.848    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[12]/C
+                         clock pessimism              0.274    15.122    
+                         clock uncertainty           -0.035    15.087    
+    SLICE_X0Y21          FDCE (Setup_fdce_C_D)        0.062    15.149    clkdiv_i/q_reg[12]
+  -------------------------------------------------------------------
+                         required time                         15.149    
+                         arrival time                          -7.491    
+  -------------------------------------------------------------------
+                         slack                                  7.658    
+
+Slack (MET) :             7.662ns  (required time - arrival time)
+  Source:                 clkdiv_i/q_reg[1]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[9]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.340ns  (logic 1.578ns (67.440%)  route 0.762ns (32.560%))
+  Logic Levels:           3  (CARRY4=3)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.148ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.627     5.148    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.456     5.604 r  clkdiv_i/q_reg[1]/Q
+                         net (fo=1, routed)           0.762     6.366    clkdiv_i/q_reg_n_0_[1]
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     7.040 r  clkdiv_i/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.040    clkdiv_i/q_reg[0]_i_1_n_0
+    SLICE_X0Y19          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.154 r  clkdiv_i/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.154    clkdiv_i/q_reg[4]_i_1_n_0
+    SLICE_X0Y20          CARRY4 (Prop_carry4_CI_O[1])
+                                                      0.334     7.488 r  clkdiv_i/q_reg[8]_i_1/O[1]
+                         net (fo=1, routed)           0.000     7.488    clkdiv_i/q_reg[8]_i_1_n_6
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[9]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.508    14.849    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[9]/C
+                         clock pessimism              0.274    15.123    
+                         clock uncertainty           -0.035    15.088    
+    SLICE_X0Y20          FDCE (Setup_fdce_C_D)        0.062    15.150    clkdiv_i/q_reg[9]
+  -------------------------------------------------------------------
+                         required time                         15.150    
+                         arrival time                          -7.488    
+  -------------------------------------------------------------------
+                         slack                                  7.662    
+
+Slack (MET) :             7.683ns  (required time - arrival time)
+  Source:                 clkdiv_i/q_reg[1]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[11]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.319ns  (logic 1.557ns (67.145%)  route 0.762ns (32.855%))
+  Logic Levels:           3  (CARRY4=3)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.148ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.627     5.148    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.456     5.604 r  clkdiv_i/q_reg[1]/Q
+                         net (fo=1, routed)           0.762     6.366    clkdiv_i/q_reg_n_0_[1]
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     7.040 r  clkdiv_i/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.040    clkdiv_i/q_reg[0]_i_1_n_0
+    SLICE_X0Y19          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.154 r  clkdiv_i/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.154    clkdiv_i/q_reg[4]_i_1_n_0
+    SLICE_X0Y20          CARRY4 (Prop_carry4_CI_O[3])
+                                                      0.313     7.467 r  clkdiv_i/q_reg[8]_i_1/O[3]
+                         net (fo=1, routed)           0.000     7.467    clkdiv_i/q_reg[8]_i_1_n_4
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[11]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.508    14.849    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[11]/C
+                         clock pessimism              0.274    15.123    
+                         clock uncertainty           -0.035    15.088    
+    SLICE_X0Y20          FDCE (Setup_fdce_C_D)        0.062    15.150    clkdiv_i/q_reg[11]
+  -------------------------------------------------------------------
+                         required time                         15.150    
+                         arrival time                          -7.467    
+  -------------------------------------------------------------------
+                         slack                                  7.683    
+
+Slack (MET) :             7.757ns  (required time - arrival time)
+  Source:                 clkdiv_i/q_reg[1]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[10]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            10.000ns  (sys_clk_pin rise@10.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        2.245ns  (logic 1.483ns (66.062%)  route 0.762ns (33.938%))
+  Logic Levels:           3  (CARRY4=3)
+  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
+    Source Clock Delay      (SCD):    5.148ns
+    Clock Pessimism Removal (CPR):    0.274ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.967     3.425    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.627     5.148    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.456     5.604 r  clkdiv_i/q_reg[1]/Q
+                         net (fo=1, routed)           0.762     6.366    clkdiv_i/q_reg_n_0_[1]
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[1]_CO[3])
+                                                      0.674     7.040 r  clkdiv_i/q_reg[0]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.040    clkdiv_i/q_reg[0]_i_1_n_0
+    SLICE_X0Y19          CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.114     7.154 r  clkdiv_i/q_reg[4]_i_1/CO[3]
+                         net (fo=1, routed)           0.000     7.154    clkdiv_i/q_reg[4]_i_1_n_0
+    SLICE_X0Y20          CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.239     7.393 r  clkdiv_i/q_reg[8]_i_1/O[2]
+                         net (fo=1, routed)           0.000     7.393    clkdiv_i/q_reg[8]_i_1_n_5
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[10]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                     10.000    10.000 r  
+    W5                                                0.000    10.000 r  clk (IN)
+                         net (fo=0)                   0.000    10.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862    13.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.508    14.849    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[10]/C
+                         clock pessimism              0.274    15.123    
+                         clock uncertainty           -0.035    15.088    
+    SLICE_X0Y20          FDCE (Setup_fdce_C_D)        0.062    15.150    clkdiv_i/q_reg[10]
+  -------------------------------------------------------------------
+                         required time                         15.150    
+                         arrival time                          -7.393    
+  -------------------------------------------------------------------
+                         slack                                  7.757    
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             0.324ns  (arrival time - required time)
+  Source:                 clkdiv_i/q_reg[0]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[0]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.429ns  (logic 0.256ns (59.730%)  route 0.173ns (40.270%))
+  Logic Levels:           2  (CARRY4=1 LUT1=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.984ns
+    Source Clock Delay      (SCD):    1.471ns
+    Clock Pessimism Removal (CPR):    0.513ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.588     1.471    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.141     1.612 f  clkdiv_i/q_reg[0]/Q
+                         net (fo=1, routed)           0.173     1.785    clkdiv_i/q_reg_n_0_[0]
+    SLICE_X0Y18          LUT1 (Prop_lut1_I0_O)        0.045     1.830 r  clkdiv_i/q[0]_i_2/O
+                         net (fo=1, routed)           0.000     1.830    clkdiv_i/q[0]_i_2_n_0
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[0]_O[0])
+                                                      0.070     1.900 r  clkdiv_i/q_reg[0]_i_1/O[0]
+                         net (fo=1, routed)           0.000     1.900    clkdiv_i/q_reg[0]_i_1_n_7
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.857     1.984    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[0]/C
+                         clock pessimism             -0.513     1.471    
+    SLICE_X0Y18          FDCE (Hold_fdce_C_D)         0.105     1.576    clkdiv_i/q_reg[0]
+  -------------------------------------------------------------------
+                         required time                         -1.576    
+                         arrival time                           1.900    
+  -------------------------------------------------------------------
+                         slack                                  0.324    
+
+Slack (MET) :             0.327ns  (arrival time - required time)
+  Source:                 clkdiv_i/q_reg[12]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[12]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.432ns  (logic 0.256ns (59.199%)  route 0.176ns (40.801%))
+  Logic Levels:           1  (CARRY4=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.981ns
+    Source Clock Delay      (SCD):    1.468ns
+    Clock Pessimism Removal (CPR):    0.513ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.585     1.468    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[12]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y21          FDCE (Prop_fdce_C_Q)         0.141     1.609 r  clkdiv_i/q_reg[12]/Q
+                         net (fo=1, routed)           0.176     1.786    clkdiv_i/q_reg_n_0_[12]
+    SLICE_X0Y21          CARRY4 (Prop_carry4_S[0]_O[0])
+                                                      0.115     1.901 r  clkdiv_i/q_reg[12]_i_1/O[0]
+                         net (fo=1, routed)           0.000     1.901    clkdiv_i/q_reg[12]_i_1_n_7
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[12]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.854     1.981    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[12]/C
+                         clock pessimism             -0.513     1.468    
+    SLICE_X0Y21          FDCE (Hold_fdce_C_D)         0.105     1.573    clkdiv_i/q_reg[12]
+  -------------------------------------------------------------------
+                         required time                         -1.573    
+                         arrival time                           1.901    
+  -------------------------------------------------------------------
+                         slack                                  0.327    
+
+Slack (MET) :             0.327ns  (arrival time - required time)
+  Source:                 clkdiv_i/q_reg[16]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[16]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.432ns  (logic 0.256ns (59.199%)  route 0.176ns (40.801%))
+  Logic Levels:           1  (CARRY4=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.980ns
+    Source Clock Delay      (SCD):    1.468ns
+    Clock Pessimism Removal (CPR):    0.512ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.585     1.468    clkdiv_i/clk
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[16]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y22          FDCE (Prop_fdce_C_Q)         0.141     1.609 r  clkdiv_i/q_reg[16]/Q
+                         net (fo=1, routed)           0.176     1.786    clkdiv_i/q_reg_n_0_[16]
+    SLICE_X0Y22          CARRY4 (Prop_carry4_S[0]_O[0])
+                                                      0.115     1.901 r  clkdiv_i/q_reg[16]_i_1/O[0]
+                         net (fo=1, routed)           0.000     1.901    clkdiv_i/q_reg[16]_i_1_n_7
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[16]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.853     1.980    clkdiv_i/clk
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[16]/C
+                         clock pessimism             -0.512     1.468    
+    SLICE_X0Y22          FDCE (Hold_fdce_C_D)         0.105     1.573    clkdiv_i/q_reg[16]
+  -------------------------------------------------------------------
+                         required time                         -1.573    
+                         arrival time                           1.901    
+  -------------------------------------------------------------------
+                         slack                                  0.327    
+
+Slack (MET) :             0.327ns  (arrival time - required time)
+  Source:                 clkdiv_i/q_reg[4]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[4]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.432ns  (logic 0.256ns (59.199%)  route 0.176ns (40.801%))
+  Logic Levels:           1  (CARRY4=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.983ns
+    Source Clock Delay      (SCD):    1.470ns
+    Clock Pessimism Removal (CPR):    0.513ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.587     1.470    clkdiv_i/clk
+    SLICE_X0Y19          FDCE                                         r  clkdiv_i/q_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y19          FDCE (Prop_fdce_C_Q)         0.141     1.611 r  clkdiv_i/q_reg[4]/Q
+                         net (fo=1, routed)           0.176     1.788    clkdiv_i/q_reg_n_0_[4]
+    SLICE_X0Y19          CARRY4 (Prop_carry4_S[0]_O[0])
+                                                      0.115     1.903 r  clkdiv_i/q_reg[4]_i_1/O[0]
+                         net (fo=1, routed)           0.000     1.903    clkdiv_i/q_reg[4]_i_1_n_7
+    SLICE_X0Y19          FDCE                                         r  clkdiv_i/q_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.856     1.983    clkdiv_i/clk
+    SLICE_X0Y19          FDCE                                         r  clkdiv_i/q_reg[4]/C
+                         clock pessimism             -0.513     1.470    
+    SLICE_X0Y19          FDCE (Hold_fdce_C_D)         0.105     1.575    clkdiv_i/q_reg[4]
+  -------------------------------------------------------------------
+                         required time                         -1.575    
+                         arrival time                           1.903    
+  -------------------------------------------------------------------
+                         slack                                  0.327    
+
+Slack (MET) :             0.327ns  (arrival time - required time)
+  Source:                 clkdiv_i/q_reg[8]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[8]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.432ns  (logic 0.256ns (59.199%)  route 0.176ns (40.801%))
+  Logic Levels:           1  (CARRY4=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.982ns
+    Source Clock Delay      (SCD):    1.469ns
+    Clock Pessimism Removal (CPR):    0.513ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.586     1.469    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[8]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y20          FDCE (Prop_fdce_C_Q)         0.141     1.610 r  clkdiv_i/q_reg[8]/Q
+                         net (fo=1, routed)           0.176     1.787    clkdiv_i/q_reg_n_0_[8]
+    SLICE_X0Y20          CARRY4 (Prop_carry4_S[0]_O[0])
+                                                      0.115     1.902 r  clkdiv_i/q_reg[8]_i_1/O[0]
+                         net (fo=1, routed)           0.000     1.902    clkdiv_i/q_reg[8]_i_1_n_7
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[8]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.855     1.982    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[8]/C
+                         clock pessimism             -0.513     1.469    
+    SLICE_X0Y20          FDCE (Hold_fdce_C_D)         0.105     1.574    clkdiv_i/q_reg[8]
+  -------------------------------------------------------------------
+                         required time                         -1.574    
+                         arrival time                           1.902    
+  -------------------------------------------------------------------
+                         slack                                  0.327    
+
+Slack (MET) :             0.360ns  (arrival time - required time)
+  Source:                 clkdiv_i/q_reg[0]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[1]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.465ns  (logic 0.292ns (62.850%)  route 0.173ns (37.150%))
+  Logic Levels:           2  (CARRY4=1 LUT1=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.984ns
+    Source Clock Delay      (SCD):    1.471ns
+    Clock Pessimism Removal (CPR):    0.513ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.588     1.471    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y18          FDCE (Prop_fdce_C_Q)         0.141     1.612 f  clkdiv_i/q_reg[0]/Q
+                         net (fo=1, routed)           0.173     1.785    clkdiv_i/q_reg_n_0_[0]
+    SLICE_X0Y18          LUT1 (Prop_lut1_I0_O)        0.045     1.830 r  clkdiv_i/q[0]_i_2/O
+                         net (fo=1, routed)           0.000     1.830    clkdiv_i/q[0]_i_2_n_0
+    SLICE_X0Y18          CARRY4 (Prop_carry4_S[0]_O[1])
+                                                      0.106     1.936 r  clkdiv_i/q_reg[0]_i_1/O[1]
+                         net (fo=1, routed)           0.000     1.936    clkdiv_i/q_reg[0]_i_1_n_6
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.857     1.984    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+                         clock pessimism             -0.513     1.471    
+    SLICE_X0Y18          FDCE (Hold_fdce_C_D)         0.105     1.576    clkdiv_i/q_reg[1]
+  -------------------------------------------------------------------
+                         required time                         -1.576    
+                         arrival time                           1.936    
+  -------------------------------------------------------------------
+                         slack                                  0.360    
+
+Slack (MET) :             0.363ns  (arrival time - required time)
+  Source:                 clkdiv_i/q_reg[12]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[13]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.468ns  (logic 0.292ns (62.334%)  route 0.176ns (37.666%))
+  Logic Levels:           1  (CARRY4=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.981ns
+    Source Clock Delay      (SCD):    1.468ns
+    Clock Pessimism Removal (CPR):    0.513ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.585     1.468    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[12]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y21          FDCE (Prop_fdce_C_Q)         0.141     1.609 r  clkdiv_i/q_reg[12]/Q
+                         net (fo=1, routed)           0.176     1.786    clkdiv_i/q_reg_n_0_[12]
+    SLICE_X0Y21          CARRY4 (Prop_carry4_S[0]_O[1])
+                                                      0.151     1.937 r  clkdiv_i/q_reg[12]_i_1/O[1]
+                         net (fo=1, routed)           0.000     1.937    clkdiv_i/q_reg[12]_i_1_n_6
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[13]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.854     1.981    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[13]/C
+                         clock pessimism             -0.513     1.468    
+    SLICE_X0Y21          FDCE (Hold_fdce_C_D)         0.105     1.573    clkdiv_i/q_reg[13]
+  -------------------------------------------------------------------
+                         required time                         -1.573    
+                         arrival time                           1.937    
+  -------------------------------------------------------------------
+                         slack                                  0.363    
+
+Slack (MET) :             0.363ns  (arrival time - required time)
+  Source:                 clkdiv_i/q_reg[16]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[17]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.468ns  (logic 0.292ns (62.334%)  route 0.176ns (37.666%))
+  Logic Levels:           1  (CARRY4=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.980ns
+    Source Clock Delay      (SCD):    1.468ns
+    Clock Pessimism Removal (CPR):    0.512ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.585     1.468    clkdiv_i/clk
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[16]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y22          FDCE (Prop_fdce_C_Q)         0.141     1.609 r  clkdiv_i/q_reg[16]/Q
+                         net (fo=1, routed)           0.176     1.786    clkdiv_i/q_reg_n_0_[16]
+    SLICE_X0Y22          CARRY4 (Prop_carry4_S[0]_O[1])
+                                                      0.151     1.937 r  clkdiv_i/q_reg[16]_i_1/O[1]
+                         net (fo=1, routed)           0.000     1.937    clkdiv_i/q_reg[16]_i_1_n_6
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[17]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.853     1.980    clkdiv_i/clk
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[17]/C
+                         clock pessimism             -0.512     1.468    
+    SLICE_X0Y22          FDCE (Hold_fdce_C_D)         0.105     1.573    clkdiv_i/q_reg[17]
+  -------------------------------------------------------------------
+                         required time                         -1.573    
+                         arrival time                           1.937    
+  -------------------------------------------------------------------
+                         slack                                  0.363    
+
+Slack (MET) :             0.363ns  (arrival time - required time)
+  Source:                 clkdiv_i/q_reg[4]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[5]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.468ns  (logic 0.292ns (62.334%)  route 0.176ns (37.666%))
+  Logic Levels:           1  (CARRY4=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.983ns
+    Source Clock Delay      (SCD):    1.470ns
+    Clock Pessimism Removal (CPR):    0.513ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.587     1.470    clkdiv_i/clk
+    SLICE_X0Y19          FDCE                                         r  clkdiv_i/q_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y19          FDCE (Prop_fdce_C_Q)         0.141     1.611 r  clkdiv_i/q_reg[4]/Q
+                         net (fo=1, routed)           0.176     1.788    clkdiv_i/q_reg_n_0_[4]
+    SLICE_X0Y19          CARRY4 (Prop_carry4_S[0]_O[1])
+                                                      0.151     1.939 r  clkdiv_i/q_reg[4]_i_1/O[1]
+                         net (fo=1, routed)           0.000     1.939    clkdiv_i/q_reg[4]_i_1_n_6
+    SLICE_X0Y19          FDCE                                         r  clkdiv_i/q_reg[5]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.856     1.983    clkdiv_i/clk
+    SLICE_X0Y19          FDCE                                         r  clkdiv_i/q_reg[5]/C
+                         clock pessimism             -0.513     1.470    
+    SLICE_X0Y19          FDCE (Hold_fdce_C_D)         0.105     1.575    clkdiv_i/q_reg[5]
+  -------------------------------------------------------------------
+                         required time                         -1.575    
+                         arrival time                           1.939    
+  -------------------------------------------------------------------
+                         slack                                  0.363    
+
+Slack (MET) :             0.363ns  (arrival time - required time)
+  Source:                 clkdiv_i/q_reg[8]/C
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Destination:            clkdiv_i/q_reg[9]/D
+                            (rising edge-triggered cell FDCE clocked by sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             sys_clk_pin
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns)
+  Data Path Delay:        0.468ns  (logic 0.292ns (62.334%)  route 0.176ns (37.666%))
+  Logic Levels:           1  (CARRY4=1)
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.982ns
+    Source Clock Delay      (SCD):    1.469ns
+    Clock Pessimism Removal (CPR):    0.513ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.631     0.858    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.586     1.469    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[8]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y20          FDCE (Prop_fdce_C_Q)         0.141     1.610 r  clkdiv_i/q_reg[8]/Q
+                         net (fo=1, routed)           0.176     1.787    clkdiv_i/q_reg_n_0_[8]
+    SLICE_X0Y20          CARRY4 (Prop_carry4_S[0]_O[1])
+                                                      0.151     1.938 r  clkdiv_i/q_reg[8]_i_1/O[1]
+                         net (fo=1, routed)           0.000     1.938    clkdiv_i/q_reg[8]_i_1_n_6
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[9]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.855     1.982    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[9]/C
+                         clock pessimism             -0.513     1.469    
+    SLICE_X0Y20          FDCE (Hold_fdce_C_D)         0.105     1.574    clkdiv_i/q_reg[9]
+  -------------------------------------------------------------------
+                         required time                         -1.574    
+                         arrival time                           1.938    
+  -------------------------------------------------------------------
+                         slack                                  0.363    
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         sys_clk_pin
+Waveform(ns):       { 0.000 5.000 }
+Period(ns):         10.000
+Sources:            { clk }
+
+Check Type        Corner  Lib Pin  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
+Min Period        n/a     BUFG/I   n/a            2.155         10.000      7.845      BUFGCTRL_X0Y0  clk_IBUF_BUFG_inst/I
+Min Period        n/a     FDCE/C   n/a            1.000         10.000      9.000      SLICE_X0Y18    clkdiv_i/q_reg[0]/C
+Min Period        n/a     FDCE/C   n/a            1.000         10.000      9.000      SLICE_X0Y20    clkdiv_i/q_reg[10]/C
+Min Period        n/a     FDCE/C   n/a            1.000         10.000      9.000      SLICE_X0Y20    clkdiv_i/q_reg[11]/C
+Min Period        n/a     FDCE/C   n/a            1.000         10.000      9.000      SLICE_X0Y21    clkdiv_i/q_reg[12]/C
+Min Period        n/a     FDCE/C   n/a            1.000         10.000      9.000      SLICE_X0Y21    clkdiv_i/q_reg[13]/C
+Min Period        n/a     FDCE/C   n/a            1.000         10.000      9.000      SLICE_X0Y21    clkdiv_i/q_reg[14]/C
+Min Period        n/a     FDCE/C   n/a            1.000         10.000      9.000      SLICE_X0Y21    clkdiv_i/q_reg[15]/C
+Min Period        n/a     FDCE/C   n/a            1.000         10.000      9.000      SLICE_X0Y22    clkdiv_i/q_reg[16]/C
+Min Period        n/a     FDCE/C   n/a            1.000         10.000      9.000      SLICE_X0Y22    clkdiv_i/q_reg[17]/C
+Low Pulse Width   Slow    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y18    clkdiv_i/q_reg[0]/C
+Low Pulse Width   Fast    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y18    clkdiv_i/q_reg[0]/C
+Low Pulse Width   Slow    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y20    clkdiv_i/q_reg[10]/C
+Low Pulse Width   Fast    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y20    clkdiv_i/q_reg[10]/C
+Low Pulse Width   Slow    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y20    clkdiv_i/q_reg[11]/C
+Low Pulse Width   Fast    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y20    clkdiv_i/q_reg[11]/C
+Low Pulse Width   Slow    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y21    clkdiv_i/q_reg[12]/C
+Low Pulse Width   Fast    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y21    clkdiv_i/q_reg[12]/C
+Low Pulse Width   Slow    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y21    clkdiv_i/q_reg[13]/C
+Low Pulse Width   Fast    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y21    clkdiv_i/q_reg[13]/C
+High Pulse Width  Slow    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y18    clkdiv_i/q_reg[0]/C
+High Pulse Width  Fast    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y18    clkdiv_i/q_reg[0]/C
+High Pulse Width  Slow    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y20    clkdiv_i/q_reg[10]/C
+High Pulse Width  Fast    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y20    clkdiv_i/q_reg[10]/C
+High Pulse Width  Slow    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y20    clkdiv_i/q_reg[11]/C
+High Pulse Width  Fast    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y20    clkdiv_i/q_reg[11]/C
+High Pulse Width  Slow    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y21    clkdiv_i/q_reg[12]/C
+High Pulse Width  Fast    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y21    clkdiv_i/q_reg[12]/C
+High Pulse Width  Slow    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y21    clkdiv_i/q_reg[13]/C
+High Pulse Width  Fast    FDCE/C   n/a            0.500         5.000       4.500      SLICE_X0Y21    clkdiv_i/q_reg[13]/C
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  
+  To Clock:  
+
+Max Delay            17 Endpoints
+Min Delay            17 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 sw[3]
+                            (input port)
+  Destination:            seg[6]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        12.707ns  (logic 5.458ns (42.952%)  route 7.249ns (57.048%))
+  Logic Levels:           4  (IBUF=1 LUT4=1 LUT6=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W17                                               0.000     0.000 r  sw[3] (IN)
+                         net (fo=0)                   0.000     0.000    sw[3]
+    W17                  IBUF (Prop_ibuf_I_O)         1.448     1.448 r  sw_IBUF[3]_inst/O
+                         net (fo=1, routed)           3.894     5.342    afficheur/sw_IBUF[3]
+    SLICE_X64Y28         LUT6 (Prop_lut6_I2_O)        0.124     5.466 r  afficheur/seg_OBUF[6]_inst_i_5/O
+                         net (fo=7, routed)           1.049     6.515    afficheur/sw_i__31[3]
+    SLICE_X64Y27         LUT4 (Prop_lut4_I3_O)        0.150     6.665 r  afficheur/seg_OBUF[6]_inst_i_1/O
+                         net (fo=1, routed)           2.307     8.972    seg_OBUF[6]
+    U7                   OBUF (Prop_obuf_I_O)         3.735    12.707 r  seg_OBUF[6]_inst/O
+                         net (fo=0)                   0.000    12.707    seg[6]
+    U7                                                                r  seg[6] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 sw[3]
+                            (input port)
+  Destination:            seg[0]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        12.337ns  (logic 5.459ns (44.251%)  route 6.878ns (55.749%))
+  Logic Levels:           4  (IBUF=1 LUT4=1 LUT6=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W17                                               0.000     0.000 r  sw[3] (IN)
+                         net (fo=0)                   0.000     0.000    sw[3]
+    W17                  IBUF (Prop_ibuf_I_O)         1.448     1.448 r  sw_IBUF[3]_inst/O
+                         net (fo=1, routed)           3.894     5.342    afficheur/sw_IBUF[3]
+    SLICE_X64Y28         LUT6 (Prop_lut6_I2_O)        0.124     5.466 r  afficheur/seg_OBUF[6]_inst_i_5/O
+                         net (fo=7, routed)           1.039     6.505    afficheur/sw_i__31[3]
+    SLICE_X64Y27         LUT4 (Prop_lut4_I1_O)        0.152     6.657 r  afficheur/seg_OBUF[0]_inst_i_1/O
+                         net (fo=1, routed)           1.945     8.602    seg_OBUF[0]
+    W7                   OBUF (Prop_obuf_I_O)         3.735    12.337 r  seg_OBUF[0]_inst/O
+                         net (fo=0)                   0.000    12.337    seg[0]
+    W7                                                                r  seg[0] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 sw[3]
+                            (input port)
+  Destination:            seg[4]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        12.219ns  (logic 5.452ns (44.621%)  route 6.767ns (55.379%))
+  Logic Levels:           4  (IBUF=1 LUT4=1 LUT6=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W17                                               0.000     0.000 f  sw[3] (IN)
+                         net (fo=0)                   0.000     0.000    sw[3]
+    W17                  IBUF (Prop_ibuf_I_O)         1.448     1.448 f  sw_IBUF[3]_inst/O
+                         net (fo=1, routed)           3.894     5.342    afficheur/sw_IBUF[3]
+    SLICE_X64Y28         LUT6 (Prop_lut6_I2_O)        0.124     5.466 f  afficheur/seg_OBUF[6]_inst_i_5/O
+                         net (fo=7, routed)           0.823     6.289    afficheur/sw_i__31[3]
+    SLICE_X64Y27         LUT4 (Prop_lut4_I0_O)        0.153     6.442 r  afficheur/seg_OBUF[4]_inst_i_1/O
+                         net (fo=1, routed)           2.050     8.492    seg_OBUF[4]
+    U5                   OBUF (Prop_obuf_I_O)         3.727    12.219 r  seg_OBUF[4]_inst/O
+                         net (fo=0)                   0.000    12.219    seg[4]
+    U5                                                                r  seg[4] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 sw[3]
+                            (input port)
+  Destination:            seg[5]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        12.021ns  (logic 5.201ns (43.264%)  route 6.820ns (56.736%))
+  Logic Levels:           4  (IBUF=1 LUT4=1 LUT6=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W17                                               0.000     0.000 r  sw[3] (IN)
+                         net (fo=0)                   0.000     0.000    sw[3]
+    W17                  IBUF (Prop_ibuf_I_O)         1.448     1.448 r  sw_IBUF[3]_inst/O
+                         net (fo=1, routed)           3.894     5.342    afficheur/sw_IBUF[3]
+    SLICE_X64Y28         LUT6 (Prop_lut6_I2_O)        0.124     5.466 r  afficheur/seg_OBUF[6]_inst_i_5/O
+                         net (fo=7, routed)           0.837     6.303    afficheur/sw_i__31[3]
+    SLICE_X64Y27         LUT4 (Prop_lut4_I2_O)        0.124     6.427 r  afficheur/seg_OBUF[5]_inst_i_1/O
+                         net (fo=1, routed)           2.090     8.517    seg_OBUF[5]
+    V5                   OBUF (Prop_obuf_I_O)         3.504    12.021 r  seg_OBUF[5]_inst/O
+                         net (fo=0)                   0.000    12.021    seg[5]
+    V5                                                                r  seg[5] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 sw[3]
+                            (input port)
+  Destination:            seg[1]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        11.918ns  (logic 5.226ns (43.848%)  route 6.692ns (56.152%))
+  Logic Levels:           4  (IBUF=1 LUT4=1 LUT6=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W17                                               0.000     0.000 r  sw[3] (IN)
+                         net (fo=0)                   0.000     0.000    sw[3]
+    W17                  IBUF (Prop_ibuf_I_O)         1.448     1.448 r  sw_IBUF[3]_inst/O
+                         net (fo=1, routed)           3.894     5.342    afficheur/sw_IBUF[3]
+    SLICE_X64Y28         LUT6 (Prop_lut6_I2_O)        0.124     5.466 r  afficheur/seg_OBUF[6]_inst_i_5/O
+                         net (fo=7, routed)           1.049     6.515    afficheur/sw_i__31[3]
+    SLICE_X64Y27         LUT4 (Prop_lut4_I3_O)        0.124     6.639 r  afficheur/seg_OBUF[1]_inst_i_1/O
+                         net (fo=1, routed)           1.749     8.388    seg_OBUF[1]
+    W6                   OBUF (Prop_obuf_I_O)         3.529    11.918 r  seg_OBUF[1]_inst/O
+                         net (fo=0)                   0.000    11.918    seg[1]
+    W6                                                                r  seg[1] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 sw[3]
+                            (input port)
+  Destination:            seg[2]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        11.914ns  (logic 5.232ns (43.910%)  route 6.683ns (56.090%))
+  Logic Levels:           4  (IBUF=1 LUT4=1 LUT6=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W17                                               0.000     0.000 r  sw[3] (IN)
+                         net (fo=0)                   0.000     0.000    sw[3]
+    W17                  IBUF (Prop_ibuf_I_O)         1.448     1.448 r  sw_IBUF[3]_inst/O
+                         net (fo=1, routed)           3.894     5.342    afficheur/sw_IBUF[3]
+    SLICE_X64Y28         LUT6 (Prop_lut6_I2_O)        0.124     5.466 r  afficheur/seg_OBUF[6]_inst_i_5/O
+                         net (fo=7, routed)           1.039     6.505    afficheur/sw_i__31[3]
+    SLICE_X64Y27         LUT4 (Prop_lut4_I3_O)        0.124     6.629 r  afficheur/seg_OBUF[2]_inst_i_1/O
+                         net (fo=1, routed)           1.750     8.379    seg_OBUF[2]
+    U8                   OBUF (Prop_obuf_I_O)         3.535    11.914 r  seg_OBUF[2]_inst/O
+                         net (fo=0)                   0.000    11.914    seg[2]
+    U8                                                                r  seg[2] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 sw[3]
+                            (input port)
+  Destination:            seg[3]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        11.842ns  (logic 5.232ns (44.182%)  route 6.610ns (55.818%))
+  Logic Levels:           4  (IBUF=1 LUT4=1 LUT6=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    W17                                               0.000     0.000 r  sw[3] (IN)
+                         net (fo=0)                   0.000     0.000    sw[3]
+    W17                  IBUF (Prop_ibuf_I_O)         1.448     1.448 r  sw_IBUF[3]_inst/O
+                         net (fo=1, routed)           3.894     5.342    afficheur/sw_IBUF[3]
+    SLICE_X64Y28         LUT6 (Prop_lut6_I2_O)        0.124     5.466 r  afficheur/seg_OBUF[6]_inst_i_5/O
+                         net (fo=7, routed)           0.823     6.289    afficheur/sw_i__31[3]
+    SLICE_X64Y27         LUT4 (Prop_lut4_I0_O)        0.124     6.413 r  afficheur/seg_OBUF[3]_inst_i_1/O
+                         net (fo=1, routed)           1.893     8.306    seg_OBUF[3]
+    V8                   OBUF (Prop_obuf_I_O)         3.536    11.842 r  seg_OBUF[3]_inst/O
+                         net (fo=0)                   0.000    11.842    seg[3]
+    V8                                                                r  seg[3] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/an_reg[3]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            an[3]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        5.909ns  (logic 4.101ns (69.408%)  route 1.808ns (30.592%))
+  Logic Levels:           2  (FDRE=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/an_reg[3]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.419     0.419 r  afficheur/an_reg[3]/Q
+                         net (fo=1, routed)           1.808     2.227    an_OBUF[3]
+    W4                   OBUF (Prop_obuf_I_O)         3.682     5.909 r  an_OBUF[3]_inst/O
+                         net (fo=0)                   0.000     5.909    an[3]
+    W4                                                                r  an[3] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/an_reg[0]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            an[0]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        5.813ns  (logic 4.097ns (70.474%)  route 1.716ns (29.526%))
+  Logic Levels:           2  (FDRE=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/an_reg[0]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.419     0.419 r  afficheur/an_reg[0]/Q
+                         net (fo=1, routed)           1.716     2.135    an_OBUF[0]
+    U2                   OBUF (Prop_obuf_I_O)         3.678     5.813 r  an_OBUF[0]_inst/O
+                         net (fo=0)                   0.000     5.813    an[0]
+    U2                                                                r  an[0] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/an_reg[2]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            an[2]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        5.784ns  (logic 4.115ns (71.148%)  route 1.669ns (28.852%))
+  Logic Levels:           2  (FDRE=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/an_reg[2]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.419     0.419 r  afficheur/an_reg[2]/Q
+                         net (fo=1, routed)           1.669     2.088    an_OBUF[2]
+    V4                   OBUF (Prop_obuf_I_O)         3.696     5.784 r  an_OBUF[2]_inst/O
+                         net (fo=0)                   0.000     5.784    an[2]
+    V4                                                                r  an[2] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 afficheur/FSM_sequential_state_reg[0]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            afficheur/an_reg[1]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.366ns  (logic 0.186ns (50.765%)  route 0.180ns (49.235%))
+  Logic Levels:           2  (FDRE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/FSM_sequential_state_reg[0]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.141     0.141 f  afficheur/FSM_sequential_state_reg[0]/Q
+                         net (fo=10, routed)          0.180     0.321    afficheur/state[0]
+    SLICE_X65Y27         LUT2 (Prop_lut2_I1_O)        0.045     0.366 r  afficheur/an[1]_i_1/O
+                         net (fo=1, routed)           0.000     0.366    afficheur/an_i[1]
+    SLICE_X65Y27         FDRE                                         r  afficheur/an_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/FSM_sequential_state_reg[0]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            afficheur/an_reg[2]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.372ns  (logic 0.192ns (51.559%)  route 0.180ns (48.441%))
+  Logic Levels:           2  (FDRE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/FSM_sequential_state_reg[0]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.141     0.141 r  afficheur/FSM_sequential_state_reg[0]/Q
+                         net (fo=10, routed)          0.180     0.321    afficheur/state[0]
+    SLICE_X65Y27         LUT2 (Prop_lut2_I0_O)        0.051     0.372 r  afficheur/an[2]_i_1/O
+                         net (fo=1, routed)           0.000     0.372    afficheur/an_i[2]
+    SLICE_X65Y27         FDRE                                         r  afficheur/an_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/FSM_sequential_state_reg[0]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            afficheur/an_reg[0]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.374ns  (logic 0.183ns (48.868%)  route 0.191ns (51.132%))
+  Logic Levels:           2  (FDRE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/FSM_sequential_state_reg[0]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.141     0.141 r  afficheur/FSM_sequential_state_reg[0]/Q
+                         net (fo=10, routed)          0.191     0.332    afficheur/state[0]
+    SLICE_X65Y27         LUT2 (Prop_lut2_I0_O)        0.042     0.374 r  afficheur/an[0]_i_1/O
+                         net (fo=1, routed)           0.000     0.374    afficheur/an_i[0]
+    SLICE_X65Y27         FDRE                                         r  afficheur/an_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/FSM_sequential_state_reg[0]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            afficheur/FSM_sequential_state_reg[0]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.377ns  (logic 0.186ns (49.274%)  route 0.191ns (50.726%))
+  Logic Levels:           2  (FDRE=1 LUT1=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/FSM_sequential_state_reg[0]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.141     0.141 f  afficheur/FSM_sequential_state_reg[0]/Q
+                         net (fo=10, routed)          0.191     0.332    afficheur/state[0]
+    SLICE_X65Y27         LUT1 (Prop_lut1_I0_O)        0.045     0.377 r  afficheur/FSM_sequential_state[0]_i_1/O
+                         net (fo=1, routed)           0.000     0.377    afficheur/next_state[0]
+    SLICE_X65Y27         FDRE                                         r  afficheur/FSM_sequential_state_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/FSM_sequential_state_reg[0]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            afficheur/an_reg[3]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.377ns  (logic 0.184ns (48.745%)  route 0.193ns (51.255%))
+  Logic Levels:           2  (FDRE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/FSM_sequential_state_reg[0]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.141     0.141 f  afficheur/FSM_sequential_state_reg[0]/Q
+                         net (fo=10, routed)          0.193     0.334    afficheur/state[0]
+    SLICE_X65Y27         LUT2 (Prop_lut2_I0_O)        0.043     0.377 r  afficheur/an[3]_i_1/O
+                         net (fo=1, routed)           0.000     0.377    afficheur/an_i[3]
+    SLICE_X65Y27         FDRE                                         r  afficheur/an_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/FSM_sequential_state_reg[0]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            afficheur/FSM_sequential_state_reg[1]/D
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.379ns  (logic 0.186ns (49.015%)  route 0.193ns (50.985%))
+  Logic Levels:           2  (FDRE=1 LUT2=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/FSM_sequential_state_reg[0]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.141     0.141 r  afficheur/FSM_sequential_state_reg[0]/Q
+                         net (fo=10, routed)          0.193     0.334    afficheur/state[0]
+    SLICE_X65Y27         LUT2 (Prop_lut2_I1_O)        0.045     0.379 r  afficheur/FSM_sequential_state[1]_i_1/O
+                         net (fo=1, routed)           0.000     0.379    afficheur/next_state[1]
+    SLICE_X65Y27         FDRE                                         r  afficheur/FSM_sequential_state_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/an_reg[1]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            an[1]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.666ns  (logic 1.341ns (80.532%)  route 0.324ns (19.468%))
+  Logic Levels:           2  (FDRE=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/an_reg[1]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.141     0.141 r  afficheur/an_reg[1]/Q
+                         net (fo=1, routed)           0.324     0.465    an_OBUF[1]
+    U4                   OBUF (Prop_obuf_I_O)         1.200     1.666 r  an_OBUF[1]_inst/O
+                         net (fo=0)                   0.000     1.666    an[1]
+    U4                                                                r  an[1] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/an_reg[2]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            an[2]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.741ns  (logic 1.405ns (80.714%)  route 0.336ns (19.286%))
+  Logic Levels:           2  (FDRE=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/an_reg[2]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.128     0.128 r  afficheur/an_reg[2]/Q
+                         net (fo=1, routed)           0.336     0.464    an_OBUF[2]
+    V4                   OBUF (Prop_obuf_I_O)         1.277     1.741 r  an_OBUF[2]_inst/O
+                         net (fo=0)                   0.000     1.741    an[2]
+    V4                                                                r  an[2] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/an_reg[0]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            an[0]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.744ns  (logic 1.386ns (79.453%)  route 0.358ns (20.547%))
+  Logic Levels:           2  (FDRE=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/an_reg[0]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.128     0.128 r  afficheur/an_reg[0]/Q
+                         net (fo=1, routed)           0.358     0.486    an_OBUF[0]
+    U2                   OBUF (Prop_obuf_I_O)         1.258     1.744 r  an_OBUF[0]_inst/O
+                         net (fo=0)                   0.000     1.744    an[0]
+    U2                                                                r  an[0] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 afficheur/an_reg[3]/C
+                            (rising edge-triggered cell FDRE)
+  Destination:            an[3]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.792ns  (logic 1.392ns (77.698%)  route 0.400ns (22.302%))
+  Logic Levels:           2  (FDRE=1 OBUF=1)
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X65Y27         FDRE                         0.000     0.000 r  afficheur/an_reg[3]/C
+    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.128     0.128 r  afficheur/an_reg[3]/Q
+                         net (fo=1, routed)           0.400     0.528    an_OBUF[3]
+    W4                   OBUF (Prop_obuf_I_O)         1.264     1.792 r  an_OBUF[3]_inst/O
+                         net (fo=0)                   0.000     1.792    an[3]
+    W4                                                                r  an[3] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  
+  To Clock:  sys_clk_pin
+
+Max Delay            19 Endpoints
+Min Delay            19 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[16]/CLR
+                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        3.276ns  (logic 1.441ns (43.994%)  route 1.835ns (56.006%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.846ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.846ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          1.835     3.276    clkdiv_i/clear
+    SLICE_X0Y22          FDCE                                         f  clkdiv_i/q_reg[16]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.505     4.846    clkdiv_i/clk
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[16]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[17]/CLR
+                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        3.276ns  (logic 1.441ns (43.994%)  route 1.835ns (56.006%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.846ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.846ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          1.835     3.276    clkdiv_i/clear
+    SLICE_X0Y22          FDCE                                         f  clkdiv_i/q_reg[17]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.505     4.846    clkdiv_i/clk
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[17]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[18]/CLR
+                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        3.276ns  (logic 1.441ns (43.994%)  route 1.835ns (56.006%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.846ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.846ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          1.835     3.276    clkdiv_i/clear
+    SLICE_X0Y22          FDCE                                         f  clkdiv_i/q_reg[18]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.505     4.846    clkdiv_i/clk
+    SLICE_X0Y22          FDCE                                         r  clkdiv_i/q_reg[18]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[12]/CLR
+                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        3.138ns  (logic 1.441ns (45.934%)  route 1.696ns (54.066%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.848ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.848ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          1.696     3.138    clkdiv_i/clear
+    SLICE_X0Y21          FDCE                                         f  clkdiv_i/q_reg[12]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.507     4.848    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[12]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[13]/CLR
+                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        3.138ns  (logic 1.441ns (45.934%)  route 1.696ns (54.066%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.848ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.848ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          1.696     3.138    clkdiv_i/clear
+    SLICE_X0Y21          FDCE                                         f  clkdiv_i/q_reg[13]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.507     4.848    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[13]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[14]/CLR
+                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        3.138ns  (logic 1.441ns (45.934%)  route 1.696ns (54.066%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.848ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.848ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          1.696     3.138    clkdiv_i/clear
+    SLICE_X0Y21          FDCE                                         f  clkdiv_i/q_reg[14]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.507     4.848    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[14]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[15]/CLR
+                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        3.138ns  (logic 1.441ns (45.934%)  route 1.696ns (54.066%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.848ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.848ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          1.696     3.138    clkdiv_i/clear
+    SLICE_X0Y21          FDCE                                         f  clkdiv_i/q_reg[15]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.507     4.848    clkdiv_i/clk
+    SLICE_X0Y21          FDCE                                         r  clkdiv_i/q_reg[15]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[10]/CLR
+                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        2.989ns  (logic 1.441ns (48.213%)  route 1.548ns (51.787%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.849ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.849ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          1.548     2.989    clkdiv_i/clear
+    SLICE_X0Y20          FDCE                                         f  clkdiv_i/q_reg[10]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.508     4.849    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[10]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[11]/CLR
+                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        2.989ns  (logic 1.441ns (48.213%)  route 1.548ns (51.787%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.849ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.849ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          1.548     2.989    clkdiv_i/clear
+    SLICE_X0Y20          FDCE                                         f  clkdiv_i/q_reg[11]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.508     4.849    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[11]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[8]/CLR
+                            (recovery check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        2.989ns  (logic 1.441ns (48.213%)  route 1.548ns (51.787%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        4.849ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.849ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         1.441     1.441 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          1.548     2.989    clkdiv_i/clear
+    SLICE_X0Y20          FDCE                                         f  clkdiv_i/q_reg[8]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         1.388     1.388 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           1.862     3.250    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     3.341 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          1.508     4.849    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[8]/C
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[0]/CLR
+                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        0.712ns  (logic 0.210ns (29.423%)  route 0.503ns (70.577%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.984ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.984ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          0.503     0.712    clkdiv_i/clear
+    SLICE_X0Y18          FDCE                                         f  clkdiv_i/q_reg[0]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.857     1.984    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[0]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[1]/CLR
+                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        0.712ns  (logic 0.210ns (29.423%)  route 0.503ns (70.577%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.984ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.984ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          0.503     0.712    clkdiv_i/clear
+    SLICE_X0Y18          FDCE                                         f  clkdiv_i/q_reg[1]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.857     1.984    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[1]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[2]/CLR
+                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        0.712ns  (logic 0.210ns (29.423%)  route 0.503ns (70.577%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.984ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.984ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          0.503     0.712    clkdiv_i/clear
+    SLICE_X0Y18          FDCE                                         f  clkdiv_i/q_reg[2]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.857     1.984    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[2]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[3]/CLR
+                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        0.712ns  (logic 0.210ns (29.423%)  route 0.503ns (70.577%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.984ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.984ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          0.503     0.712    clkdiv_i/clear
+    SLICE_X0Y18          FDCE                                         f  clkdiv_i/q_reg[3]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.857     1.984    clkdiv_i/clk
+    SLICE_X0Y18          FDCE                                         r  clkdiv_i/q_reg[3]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[4]/CLR
+                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        0.775ns  (logic 0.210ns (27.022%)  route 0.566ns (72.978%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.983ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.983ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          0.566     0.775    clkdiv_i/clear
+    SLICE_X0Y19          FDCE                                         f  clkdiv_i/q_reg[4]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.856     1.983    clkdiv_i/clk
+    SLICE_X0Y19          FDCE                                         r  clkdiv_i/q_reg[4]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[5]/CLR
+                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        0.775ns  (logic 0.210ns (27.022%)  route 0.566ns (72.978%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.983ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.983ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          0.566     0.775    clkdiv_i/clear
+    SLICE_X0Y19          FDCE                                         f  clkdiv_i/q_reg[5]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.856     1.983    clkdiv_i/clk
+    SLICE_X0Y19          FDCE                                         r  clkdiv_i/q_reg[5]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[6]/CLR
+                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        0.775ns  (logic 0.210ns (27.022%)  route 0.566ns (72.978%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.983ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.983ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          0.566     0.775    clkdiv_i/clear
+    SLICE_X0Y19          FDCE                                         f  clkdiv_i/q_reg[6]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.856     1.983    clkdiv_i/clk
+    SLICE_X0Y19          FDCE                                         r  clkdiv_i/q_reg[6]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[7]/CLR
+                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        0.775ns  (logic 0.210ns (27.022%)  route 0.566ns (72.978%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.983ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.983ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          0.566     0.775    clkdiv_i/clear
+    SLICE_X0Y19          FDCE                                         f  clkdiv_i/q_reg[7]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.856     1.983    clkdiv_i/clk
+    SLICE_X0Y19          FDCE                                         r  clkdiv_i/q_reg[7]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[10]/CLR
+                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        0.839ns  (logic 0.210ns (24.983%)  route 0.629ns (75.017%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.982ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.982ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          0.629     0.839    clkdiv_i/clear
+    SLICE_X0Y20          FDCE                                         f  clkdiv_i/q_reg[10]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.855     1.982    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[10]/C
+
+Slack:                    inf
+  Source:                 reset
+                            (input port)
+  Destination:            clkdiv_i/q_reg[11]/CLR
+                            (removal check against rising-edge clock sys_clk_pin  {rise@0.000ns fall@5.000ns period=10.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        0.839ns  (logic 0.210ns (24.983%)  route 0.629ns (75.017%))
+  Logic Levels:           1  (IBUF=1)
+  Clock Path Skew:        1.982ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.982ns
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    U18                                               0.000     0.000 f  reset (IN)
+                         net (fo=0)                   0.000     0.000    reset
+    U18                  IBUF (Prop_ibuf_I_O)         0.210     0.210 f  reset_IBUF_inst/O
+                         net (fo=19, routed)          0.629     0.839    clkdiv_i/clear
+    SLICE_X0Y20          FDCE                                         f  clkdiv_i/q_reg[11]/CLR
+  -------------------------------------------------------------------    -------------------
+
+                         (clock sys_clk_pin rise edge)
+                                                      0.000     0.000 r  
+    W5                                                0.000     0.000 r  clk (IN)
+                         net (fo=0)                   0.000     0.000    clk
+    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
+                         net (fo=1, routed)           0.685     1.099    clk_IBUF
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
+                         net (fo=19, routed)          0.855     1.982    clkdiv_i/clk
+    SLICE_X0Y20          FDCE                                         r  clkdiv_i/q_reg[11]/C
+
+
+
+
+
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_utilization_placed.pb b/tp_6/tp_6.runs/impl_1/top_afficheur_utilization_placed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..00840ca3fb1f7e2548506f465eb9b754c455b925
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/top_afficheur_utilization_placed.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/top_afficheur_utilization_placed.rpt b/tp_6/tp_6.runs/impl_1/top_afficheur_utilization_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..d98b56f6ae70aa46900ee482965cd195d8dc84d1
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/top_afficheur_utilization_placed.rpt
@@ -0,0 +1,214 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 12:08:04 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_utilization -file top_afficheur_utilization_placed.rpt -pb top_afficheur_utilization_placed.pb
+| Design       : top_afficheur
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+|        Site Type        | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs              |   12 |     0 |          0 |     20800 |  0.06 |
+|   LUT as Logic          |   12 |     0 |          0 |     20800 |  0.06 |
+|   LUT as Memory         |    0 |     0 |          0 |      9600 |  0.00 |
+| Slice Registers         |   25 |     0 |          0 |     41600 |  0.06 |
+|   Register as Flip Flop |   25 |     0 |          0 |     41600 |  0.06 |
+|   Register as Latch     |    0 |     0 |          0 |     41600 |  0.00 |
+| F7 Muxes                |    0 |     0 |          0 |     16300 |  0.00 |
+| F8 Muxes                |    0 |     0 |          0 |      8150 |  0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 19    |          Yes |           - |        Reset |
+| 0     |          Yes |         Set |            - |
+| 6     |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++------------------------------------------+------+-------+------------+-----------+-------+
+|                 Site Type                | Used | Fixed | Prohibited | Available | Util% |
++------------------------------------------+------+-------+------------+-----------+-------+
+| Slice                                    |    9 |     0 |          0 |      8150 |  0.11 |
+|   SLICEL                                 |    7 |     0 |            |           |       |
+|   SLICEM                                 |    2 |     0 |            |           |       |
+| LUT as Logic                             |   12 |     0 |          0 |     20800 |  0.06 |
+|   using O5 output only                   |    0 |       |            |           |       |
+|   using O6 output only                   |    6 |       |            |           |       |
+|   using O5 and O6                        |    6 |       |            |           |       |
+| LUT as Memory                            |    0 |     0 |          0 |      9600 |  0.00 |
+|   LUT as Distributed RAM                 |    0 |     0 |            |           |       |
+|     using O5 output only                 |    0 |       |            |           |       |
+|     using O6 output only                 |    0 |       |            |           |       |
+|     using O5 and O6                      |    0 |       |            |           |       |
+|   LUT as Shift Register                  |    0 |     0 |            |           |       |
+|     using O5 output only                 |    0 |       |            |           |       |
+|     using O6 output only                 |    0 |       |            |           |       |
+|     using O5 and O6                      |    0 |       |            |           |       |
+| Slice Registers                          |   25 |     0 |          0 |     41600 |  0.06 |
+|   Register driven from within the Slice  |   25 |       |            |           |       |
+|   Register driven from outside the Slice |    0 |       |            |           |       |
+| Unique Control Sets                      |    2 |       |          0 |      8150 |  0.02 |
++------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile |    0 |     0 |          0 |        50 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |          0 |        50 |  0.00 |
+|   RAMB18       |    0 |     0 |          0 |       100 |  0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |        90 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |   29 |    29 |          0 |       106 | 27.36 |
+|   IOB Master Pads           |   14 |       |            |           |       |
+|   IOB Slave Pads            |   15 |       |            |           |       |
+| Bonded IPADs                |    0 |     0 |          0 |        10 |  0.00 |
+| Bonded OPADs                |    0 |     0 |          0 |         4 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |         5 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |         5 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |        20 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |        20 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |          0 |         5 |  0.00 |
+| IBUFDS                      |    0 |     0 |          0 |       104 |  0.00 |
+| GTPE2_CHANNEL               |    0 |     0 |          0 |         2 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |        20 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |        20 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |          0 |       250 |  0.00 |
+| IBUFDS_GTE2                 |    0 |     0 |          0 |         2 |  0.00 |
+| ILOGIC                      |    0 |     0 |          0 |       106 |  0.00 |
+| OLOGIC                      |    0 |     0 |          0 |       106 |  0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+|  Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL   |    1 |     0 |          0 |        32 |  3.13 |
+| BUFIO      |    0 |     0 |          0 |        20 |  0.00 |
+| MMCME2_ADV |    0 |     0 |          0 |         5 |  0.00 |
+| PLLE2_ADV  |    0 |     0 |          0 |         5 |  0.00 |
+| BUFMRCE    |    0 |     0 |          0 |        10 |  0.00 |
+| BUFHCE     |    0 |     0 |          0 |        72 |  0.00 |
+| BUFR       |    0 |     0 |          0 |        20 |  0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |          0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE     |   19 |        Flop & Latch |
+| IBUF     |   18 |                  IO |
+| OBUF     |   11 |                  IO |
+| LUT4     |    7 |                 LUT |
+| FDRE     |    6 |        Flop & Latch |
+| LUT2     |    5 |                 LUT |
+| CARRY4   |    5 |          CarryLogic |
+| LUT6     |    4 |                 LUT |
+| LUT1     |    2 |                 LUT |
+| BUFG     |    1 |               Clock |
++----------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/tp_6/tp_6.runs/impl_1/vivado.jou b/tp_6/tp_6.runs/impl_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..818c45a43af7566df2155a0c735215c3afc67e75
--- /dev/null
+++ b/tp_6/tp_6.runs/impl_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Apr 29 12:06:52 2025
+# Process ID         : 4340
+# Current directory  : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1
+# Command line       : vivado.exe -log top_afficheur.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top_afficheur.tcl -notrace
+# Log file           : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1/top_afficheur.vdi
+# Journal file       : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/impl_1\vivado.jou
+# Running On         : LAPTOP-RU5MPQFG
+# Platform           : Windows Server 2016 or Windows 10
+# Operating System   : 26100
+# Processor Detail   : AMD Ryzen 5 5500U with Radeon Graphics         
+# CPU Frequency      : 2096 MHz
+# CPU Physical cores : 6
+# CPU Logical cores  : 12
+# Host memory        : 16468 MB
+# Swap memory        : 1073 MB
+# Total Virtual      : 17542 MB
+# Available Virtual  : 8620 MB
+#-----------------------------------------------------------
+source top_afficheur.tcl -notrace
diff --git a/tp_6/tp_6.runs/impl_1/vivado.pb b/tp_6/tp_6.runs/impl_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..62ad5fee07c4857a13eb1d8e692d98ee33fbf669
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/vivado.pb differ
diff --git a/tp_6/tp_6.runs/impl_1/write_bitstream.pb b/tp_6/tp_6.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000000000000000000000000000000000000..2ca2447ebe1c9dd59d4821d2687b7b5b7d1ca2e4
Binary files /dev/null and b/tp_6/tp_6.runs/impl_1/write_bitstream.pb differ
diff --git a/tp_6/tp_6.runs/synth_1/.Xil/top_afficheur_propImpl.xdc b/tp_6/tp_6.runs/synth_1/.Xil/top_afficheur_propImpl.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..0dded62e760e403b49d1cc54af1076b2a724790f
--- /dev/null
+++ b/tp_6/tp_6.runs/synth_1/.Xil/top_afficheur_propImpl.xdc
@@ -0,0 +1,63 @@
+set_property SRC_FILE_INFO {cfile:C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc rfile:../../../tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W5 [get_ports clk]
+set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U18 [get_ports reset]
+set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
+set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
+set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
+set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
+set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
+set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
+set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
+set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
+set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
+set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
+set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
+set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
+set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
+set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
+set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
+set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
+set_property src_info {type:XDC file:1 line:85 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
+set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
+set_property src_info {type:XDC file:1 line:89 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
+set_property src_info {type:XDC file:1 line:91 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
+set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
+set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
+set_property src_info {type:XDC file:1 line:97 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
+set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V7 [get_ports dp]
+set_property src_info {type:XDC file:1 line:101 export:INPUT save:INPUT read:READ} [current_design]
+set_property IOSTANDARD LVCMOS33 [get_ports dp]
+set_property src_info {type:XDC file:1 line:103 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U2 [get_ports {an[0]}]
+set_property src_info {type:XDC file:1 line:105 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U4 [get_ports {an[1]}]
+set_property src_info {type:XDC file:1 line:107 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V4 [get_ports {an[2]}]
+set_property src_info {type:XDC file:1 line:109 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN W4 [get_ports {an[3]}]
diff --git a/tp_6/tp_6.runs/synth_1/gen_run.xml b/tp_6/tp_6.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0a7de706d828632739713a09ae00f2037bf98525
--- /dev/null
+++ b/tp_6/tp_6.runs/synth_1/gen_run.xml
@@ -0,0 +1,91 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1745921097" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top_afficheur.dcp">
+  <File Type="PA-TCL" Name="top_afficheur.tcl"/>
+  <File Type="REPORTS-TCL" Name="top_afficheur_reports.tcl"/>
+  <File Type="RDS-RDS" Name="top_afficheur.vds"/>
+  <File Type="RDS-PROPCONSTRS" Name="top_afficheur_drc_synth.rpt"/>
+  <File Type="RDS-UTIL" Name="top_afficheur_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="top_afficheur_utilization_synth.pb"/>
+  <File Type="RDS-DCP" Name="top_afficheur.dcp"/>
+  <File Type="VDS-TIMINGSUMMARY" Name="top_afficheur_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="top_afficheur_timing_summary_synth.pb"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PSRCDIR/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd"/>
+        <Attr Name="ImportTime" Val="1745867194"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/new/afficheur_16.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd"/>
+        <Attr Name="ImportTime" Val="1744632998"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/new/top_afficheur.vhd">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PSRCDIR/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd">
+      <FileInfo>
+        <Attr Name="AutoDisabled" Val="1"/>
+        <Attr Name="ImportPath" Val="$PPRDIR/../tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd"/>
+        <Attr Name="ImportTime" Val="1745865959"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="top_afficheur"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys3_Master.xdc">
+      <FileInfo>
+        <Attr Name="ImportPath" Val="$PPRDIR/../tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc"/>
+        <Attr Name="ImportTime" Val="1745865959"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+    <Filter Type="Utils"/>
+    <File Path="$PSRCDIR/utils_1/imports/synth_1/top_afficheur.dcp">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedInSteps" Val="synth_1"/>
+        <Attr Name="AutoDcp" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+      <Desc>Vivado Synthesis Defaults</Desc>
+    </StratHandle>
+    <Step Id="synth_design"/>
+  </Strategy>
+</GenRun>
diff --git a/tp_6/tp_6.runs/synth_1/htr.txt b/tp_6/tp_6.runs/synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fb98b53d2d9f556ef117b25b7a5d7fe8dafc8eae
--- /dev/null
+++ b/tp_6/tp_6.runs/synth_1/htr.txt
@@ -0,0 +1,10 @@
+REM
+REM Vivado(TM)
+REM htr.txt: a Vivado-generated description of how-to-repeat the
+REM          the basic steps of a run.  Note that runme.bat/sh needs
+REM          to be invoked for Vivado to track run status.
+REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+REM
+
+vivado -log top_afficheur.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_afficheur.tcl
diff --git a/tp_6/tp_6.runs/synth_1/incr_synth_reason.pb b/tp_6/tp_6.runs/synth_1/incr_synth_reason.pb
new file mode 100644
index 0000000000000000000000000000000000000000..4cb4ed43e865edf4e8dcb3c9857bfe8acfc68b23
--- /dev/null
+++ b/tp_6/tp_6.runs/synth_1/incr_synth_reason.pb
@@ -0,0 +1 @@
+�6No compile time benefit to using incremental synthesis
\ No newline at end of file
diff --git a/tp_6/tp_6.runs/synth_1/top_afficheur.dcp b/tp_6/tp_6.runs/synth_1/top_afficheur.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..f8b015179e5aadbe71c6e1a6166fde5f561bfe51
Binary files /dev/null and b/tp_6/tp_6.runs/synth_1/top_afficheur.dcp differ
diff --git a/tp5_n/tp5_n.runs/synth_1/anti_rebond.tcl b/tp_6/tp_6.runs/synth_1/top_afficheur.tcl
similarity index 66%
rename from tp5_n/tp5_n.runs/synth_1/anti_rebond.tcl
rename to tp_6/tp_6.runs/synth_1/top_afficheur.tcl
index 19fed3a35f47480a07bcd97a86d1ee5383a9e58b..3480302540f03b018526688ec2ad868f5f06a8e7 100644
--- a/tp5_n/tp5_n.runs/synth_1/anti_rebond.tcl
+++ b/tp_6/tp_6.runs/synth_1/top_afficheur.tcl
@@ -4,7 +4,7 @@
 
 set TIME_start [clock seconds] 
 namespace eval ::optrace {
-  variable script "/home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.runs/synth_1/anti_rebond.tcl"
+  variable script "C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1/top_afficheur.tcl"
   variable category "vivado_synth"
 }
 
@@ -55,46 +55,30 @@ if {$::dispatch::connected} {
   }
 }
 
-proc create_report { reportName command } {
-  set status "."
-  append status $reportName ".fail"
-  if { [file exists $status] } {
-    eval file delete [glob $status]
-  }
-  send_msg_id runtcl-4 info "Executing : $command"
-  set retval [eval catch { $command } msg]
-  if { $retval != 0 } {
-    set fp [open $status w]
-    close $fp
-    send_msg_id runtcl-5 warning "$msg"
-  }
-}
 OPTRACE "synth_1" START { ROLLUP_AUTO }
-set_param chipscope.maxJobs 1
-set_param checkpoint.writeSynthRtdsInDcp 1
+set_param chipscope.maxJobs 3
 set_param xicom.use_bs_reader 1
-set_param synth.incrementalSynthesisCache ./.Xil/Vivado-421777-b04p9/incrSyn
-set_msg_config -id {Synth 8-256} -limit 10000
-set_msg_config -id {Synth 8-638} -limit 10000
 OPTRACE "Creating in-memory project" START { }
 create_project -in_memory -part xc7a35tcpg236-1
 
 set_param project.singleFileAddWarning.threshold 0
 set_param project.compositeFile.enableAutoGeneration 0
 set_param synth.vivado.isSynthRun true
-set_property webtalk.parent_dir /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.cache/wt [current_project]
-set_property parent.project_path /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.xpr [current_project]
+set_property webtalk.parent_dir C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.cache/wt [current_project]
+set_property parent.project_path C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.xpr [current_project]
 set_property default_lib xil_defaultlib [current_project]
-set_property target_language VHDL [current_project]
-set_property ip_output_repo /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.cache/ip [current_project]
+set_property target_language Verilog [current_project]
+set_property board_part_repo_paths {C:/Users/mamad/AppData/Roaming/Xilinx/Vivado/2024.2/xhub/board_store/xilinx_board_store} [current_project]
+set_property board_part digilentinc.com:basys3:part0:1.2 [current_project]
+set_property ip_output_repo c:/Users/mamad/INFO/hardware_design/tp_6/tp_6.cache/ip [current_project]
 set_property ip_cache_permissions {read write} [current_project]
 OPTRACE "Creating in-memory project" END { }
 OPTRACE "Adding files" START { }
 read_vhdl -library xil_defaultlib {
-  /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/digi_code.vhd
-  /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd
-  /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/fpde.vhd
-  /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/sources_1/new/fpd.vhd
+  C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd
+  C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/afficheur_16.vhd
+  C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd
+  C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/top_afficheur.vhd
 }
 OPTRACE "Adding files" END { }
 # Mark all dcp files as not used in implementation to prevent them from being
@@ -105,14 +89,16 @@ OPTRACE "Adding files" END { }
 foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
   set_property used_in_implementation false $dcp
 }
-read_xdc /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc
-set_property used_in_implementation false [get_files /home/m1io/mamadulamarana.bah.etu/tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+read_xdc C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc
+set_property used_in_implementation false [get_files C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
 
 set_param ips.enableIPCacheLiteLoad 1
+
+read_checkpoint -auto_incremental -incremental C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/utils_1/imports/synth_1/top_afficheur.dcp
 close [open __synthesis_is_running__ w]
 
 OPTRACE "synth_design" START { }
-synth_design -top anti_rebond -part xc7a35tcpg236-1
+synth_design -top top_afficheur -part xc7a35tcpg236-1
 OPTRACE "synth_design" END { }
 if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
  send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
@@ -122,10 +108,10 @@ if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
 OPTRACE "write_checkpoint" START { CHECKPOINT }
 # disable binary constraint mode for synth run checkpoints
 set_param constraints.enableBinaryConstraints false
-write_checkpoint -force -noxdef anti_rebond.dcp
+write_checkpoint -force -noxdef top_afficheur.dcp
 OPTRACE "write_checkpoint" END { }
 OPTRACE "synth reports" START { REPORT }
-create_report "synth_1_synth_report_utilization_0" "report_utilization -file anti_rebond_utilization_synth.rpt -pb anti_rebond_utilization_synth.pb"
+generate_parallel_reports -reports { "report_utilization -file top_afficheur_utilization_synth.rpt -pb top_afficheur_utilization_synth.pb"  } 
 OPTRACE "synth reports" END { }
 file delete __synthesis_is_running__
 close [open __synthesis_is_complete__ w]
diff --git a/tp_6/tp_6.runs/synth_1/top_afficheur.vds b/tp_6/tp_6.runs/synth_1/top_afficheur.vds
new file mode 100644
index 0000000000000000000000000000000000000000..c616e5b80d6a922bd6194aeaa648ab3419b4a2ab
--- /dev/null
+++ b/tp_6/tp_6.runs/synth_1/top_afficheur.vds
@@ -0,0 +1,280 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Apr 29 12:05:06 2025
+# Process ID         : 3448
+# Current directory  : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1
+# Command line       : vivado.exe -log top_afficheur.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_afficheur.tcl
+# Log file           : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1/top_afficheur.vds
+# Journal file       : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1\vivado.jou
+# Running On         : LAPTOP-RU5MPQFG
+# Platform           : Windows Server 2016 or Windows 10
+# Operating System   : 26100
+# Processor Detail   : AMD Ryzen 5 5500U with Radeon Graphics         
+# CPU Frequency      : 2096 MHz
+# CPU Physical cores : 6
+# CPU Logical cores  : 12
+# Host memory        : 16468 MB
+# Swap memory        : 1073 MB
+# Total Virtual      : 17542 MB
+# Available Virtual  : 8556 MB
+#-----------------------------------------------------------
+source top_afficheur.tcl -notrace
+Command: read_checkpoint -auto_incremental -incremental C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/utils_1/imports/synth_1/top_afficheur.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/utils_1/imports/synth_1/top_afficheur.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top top_afficheur -part xc7a35tcpg236-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
+INFO: [Device 21-403] Loading part xc7a35tcpg236-1
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 5020
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 997.977 ; gain = 468.984
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'top_afficheur' [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/top_afficheur.vhd:14]
+INFO: [Synth 8-3491] module 'clkdiv' declared at 'C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd:34' bound to instance 'clkdiv_i' of component 'clkdiv' [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/top_afficheur.vhd:41]
+INFO: [Synth 8-638] synthesizing module 'clkdiv' [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd:42]
+INFO: [Synth 8-256] done synthesizing module 'clkdiv' (0#1) [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd:42]
+WARNING: [Synth 8-5640] Port 'reset' is missing in component declaration [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/top_afficheur.vhd:29]
+INFO: [Synth 8-3491] module 'afficheur_16bits' declared at 'C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/afficheur_16.vhd:4' bound to instance 'afficheur' of component 'afficheur_16bits' [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/top_afficheur.vhd:50]
+INFO: [Synth 8-638] synthesizing module 'afficheur_16bits' [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/afficheur_16.vhd:14]
+INFO: [Synth 8-226] default block is never used [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/afficheur_16.vhd:52]
+INFO: [Synth 8-226] default block is never used [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/afficheur_16.vhd:75]
+INFO: [Synth 8-3491] module 'x7seg' declared at 'C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd:34' bound to instance 'x7seg_inst' of component 'x7seg' [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/afficheur_16.vhd:90]
+INFO: [Synth 8-638] synthesizing module 'x7seg' [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd:40]
+INFO: [Synth 8-226] default block is never used [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd:57]
+INFO: [Synth 8-256] done synthesizing module 'x7seg' (0#1) [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd:40]
+INFO: [Synth 8-256] done synthesizing module 'afficheur_16bits' (0#1) [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/afficheur_16.vhd:14]
+INFO: [Synth 8-256] done synthesizing module 'top_afficheur' (0#1) [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/new/top_afficheur.vhd:14]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1102.840 ; gain = 573.848
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1102.840 ; gain = 573.848
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1102.840 ; gain = 573.848
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.840 ; gain = 0.000
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+WARNING: [Vivado 12-584] No ports matched 'dp'. [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:100]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:100]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+WARNING: [Vivado 12-584] No ports matched 'dp'. [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:101]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc:101]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_afficheur_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/top_afficheur_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1172.578 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1172.578 ; gain = 0.000
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 1172.578 ; gain = 643.586
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a35tcpg236-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 1172.578 ; gain = 643.586
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 1172.578 ; gain = 643.586
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'afficheur_16bits'
+WARNING: [Synth 8-327] inferring latch for variable 'seg_x7_reg' [C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd:59]
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              st1_digit1 |                               00 |                               00
+              st2_digit2 |                               01 |                               01
+              st3_digit3 |                               10 |                               10
+              st4_digit4 |                               11 |                               11
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'afficheur_16bits'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 1172.578 ; gain = 643.586
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input   24 Bit       Adders := 1     
++---Registers : 
+	                4 Bit    Registers := 1     
+	                1 Bit    Registers := 1     
++---Muxes : 
+	   3 Input    7 Bit        Muxes := 1     
+	   4 Input    4 Bit        Muxes := 2     
+	   4 Input    2 Bit        Muxes := 1     
+	  16 Input    1 Bit        Muxes := 1     
+	   4 Input    1 Bit        Muxes := 1     
+	   2 Input    1 Bit        Muxes := 1     
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 90 (col length:60)
+BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+WARNING: [Synth 8-3332] Sequential element (afficheur/x7seg_inst/seg_x7_reg[6]) is unused and will be removed from module top_afficheur.
+WARNING: [Synth 8-3332] Sequential element (afficheur/x7seg_inst/seg_x7_reg[5]) is unused and will be removed from module top_afficheur.
+WARNING: [Synth 8-3332] Sequential element (afficheur/x7seg_inst/seg_x7_reg[4]) is unused and will be removed from module top_afficheur.
+WARNING: [Synth 8-3332] Sequential element (afficheur/x7seg_inst/seg_x7_reg[3]) is unused and will be removed from module top_afficheur.
+WARNING: [Synth 8-3332] Sequential element (afficheur/x7seg_inst/seg_x7_reg[2]) is unused and will be removed from module top_afficheur.
+WARNING: [Synth 8-3332] Sequential element (afficheur/x7seg_inst/seg_x7_reg[1]) is unused and will be removed from module top_afficheur.
+WARNING: [Synth 8-3332] Sequential element (afficheur/x7seg_inst/seg_x7_reg[0]) is unused and will be removed from module top_afficheur.
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 1172.578 ; gain = 643.586
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:53 ; elapsed = 00:00:57 . Memory (MB): peak = 1302.949 ; gain = 773.957
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:53 ; elapsed = 00:00:57 . Memory (MB): peak = 1303.023 ; gain = 774.031
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:53 ; elapsed = 00:00:57 . Memory (MB): peak = 1314.113 ; gain = 785.121
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:01:03 ; elapsed = 00:01:08 . Memory (MB): peak = 1529.676 ; gain = 1000.684
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:01:03 ; elapsed = 00:01:08 . Memory (MB): peak = 1529.676 ; gain = 1000.684
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:03 ; elapsed = 00:01:08 . Memory (MB): peak = 1529.676 ; gain = 1000.684
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:01:03 ; elapsed = 00:01:08 . Memory (MB): peak = 1529.676 ; gain = 1000.684
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:01:03 ; elapsed = 00:01:08 . Memory (MB): peak = 1529.676 ; gain = 1000.684
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:01:03 ; elapsed = 00:01:08 . Memory (MB): peak = 1529.676 ; gain = 1000.684
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------+------+
+|      |Cell   |Count |
++------+-------+------+
+|1     |BUFG   |     1|
+|2     |CARRY4 |     5|
+|3     |LUT1   |     2|
+|4     |LUT2   |     5|
+|5     |LUT4   |     7|
+|6     |LUT6   |     4|
+|7     |FDCE   |    19|
+|8     |FDRE   |     6|
+|9     |IBUF   |    18|
+|10    |OBUF   |    11|
++------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:01:03 ; elapsed = 00:01:08 . Memory (MB): peak = 1529.676 ; gain = 1000.684
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 9 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:01:04 . Memory (MB): peak = 1529.676 ; gain = 930.945
+Synthesis Optimization Complete : Time (s): cpu = 00:01:03 ; elapsed = 00:01:08 . Memory (MB): peak = 1529.676 ; gain = 1000.684
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1529.676 ; gain = 0.000
+INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1529.676 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete | Checksum: d688bf7f
+INFO: [Common 17-83] Releasing license: Synthesis
+37 Infos, 12 Warnings, 2 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:01:12 ; elapsed = 00:01:23 . Memory (MB): peak = 1529.676 ; gain = 1190.875
+INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1529.676 ; gain = 0.000
+INFO: [Common 17-1381] The checkpoint 'C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1/top_afficheur.dcp' has been generated.
+INFO: [Vivado 12-24828] Executing command : report_utilization -file top_afficheur_utilization_synth.rpt -pb top_afficheur_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Tue Apr 29 12:06:41 2025...
diff --git a/tp_6/tp_6.runs/synth_1/top_afficheur_utilization_synth.pb b/tp_6/tp_6.runs/synth_1/top_afficheur_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..00840ca3fb1f7e2548506f465eb9b754c455b925
Binary files /dev/null and b/tp_6/tp_6.runs/synth_1/top_afficheur_utilization_synth.pb differ
diff --git a/tp_6/tp_6.runs/synth_1/top_afficheur_utilization_synth.rpt b/tp_6/tp_6.runs/synth_1/top_afficheur_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..90fee99409a2d381d40fdc1fa969fc246f70cdd7
--- /dev/null
+++ b/tp_6/tp_6.runs/synth_1/top_afficheur_utilization_synth.rpt
@@ -0,0 +1,183 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
+| Date         : Tue Apr 29 12:06:41 2025
+| Host         : LAPTOP-RU5MPQFG running 64-bit major release  (build 9200)
+| Command      : report_utilization -file top_afficheur_utilization_synth.rpt -pb top_afficheur_utilization_synth.pb
+| Design       : top_afficheur
+| Device       : xc7a35tcpg236-1
+| Speed File   : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+|        Site Type        | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs*             |   12 |     0 |          0 |     20800 |  0.06 |
+|   LUT as Logic          |   12 |     0 |          0 |     20800 |  0.06 |
+|   LUT as Memory         |    0 |     0 |          0 |      9600 |  0.00 |
+| Slice Registers         |   25 |     0 |          0 |     41600 |  0.06 |
+|   Register as Flip Flop |   25 |     0 |          0 |     41600 |  0.06 |
+|   Register as Latch     |    0 |     0 |          0 |     41600 |  0.00 |
+| F7 Muxes                |    0 |     0 |          0 |     16300 |  0.00 |
+| F8 Muxes                |    0 |     0 |          0 |      8150 |  0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+Warning! For any ECO changes, please run place_design if there are unplaced instances
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 19    |          Yes |           - |        Reset |
+| 0     |          Yes |         Set |            - |
+| 6     |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile |    0 |     0 |          0 |        50 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |          0 |        50 |  0.00 |
+|   RAMB18       |    0 |     0 |          0 |       100 |  0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |        90 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |   29 |     0 |          0 |       106 | 27.36 |
+| Bonded IPADs                |    0 |     0 |          0 |        10 |  0.00 |
+| Bonded OPADs                |    0 |     0 |          0 |         4 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |         5 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |         5 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |        20 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |        20 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |          0 |         5 |  0.00 |
+| IBUFDS                      |    0 |     0 |          0 |       104 |  0.00 |
+| GTPE2_CHANNEL               |    0 |     0 |          0 |         2 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |        20 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |        20 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |          0 |       250 |  0.00 |
+| IBUFDS_GTE2                 |    0 |     0 |          0 |         2 |  0.00 |
+| ILOGIC                      |    0 |     0 |          0 |       106 |  0.00 |
+| OLOGIC                      |    0 |     0 |          0 |       106 |  0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+|  Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL   |    1 |     0 |          0 |        32 |  3.13 |
+| BUFIO      |    0 |     0 |          0 |        20 |  0.00 |
+| MMCME2_ADV |    0 |     0 |          0 |         5 |  0.00 |
+| PLLE2_ADV  |    0 |     0 |          0 |         5 |  0.00 |
+| BUFMRCE    |    0 |     0 |          0 |        10 |  0.00 |
+| BUFHCE     |    0 |     0 |          0 |        72 |  0.00 |
+| BUFR       |    0 |     0 |          0 |        20 |  0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |          0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| FDCE     |   19 |        Flop & Latch |
+| IBUF     |   18 |                  IO |
+| OBUF     |   11 |                  IO |
+| LUT4     |    7 |                 LUT |
+| FDRE     |    6 |        Flop & Latch |
+| LUT2     |    5 |                 LUT |
+| CARRY4   |    5 |          CarryLogic |
+| LUT6     |    4 |                 LUT |
+| LUT1     |    2 |                 LUT |
+| BUFG     |    1 |               Clock |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/tp_6/tp_6.runs/synth_1/vivado.jou b/tp_6/tp_6.runs/synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..9b5683099266da6f95588e1b4db7381606ff8834
--- /dev/null
+++ b/tp_6/tp_6.runs/synth_1/vivado.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.2 (64-bit)
+# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024
+# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
+# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
+# Start of session at: Tue Apr 29 12:05:06 2025
+# Process ID         : 3448
+# Current directory  : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1
+# Command line       : vivado.exe -log top_afficheur.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_afficheur.tcl
+# Log file           : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1/top_afficheur.vds
+# Journal file       : C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.runs/synth_1\vivado.jou
+# Running On         : LAPTOP-RU5MPQFG
+# Platform           : Windows Server 2016 or Windows 10
+# Operating System   : 26100
+# Processor Detail   : AMD Ryzen 5 5500U with Radeon Graphics         
+# CPU Frequency      : 2096 MHz
+# CPU Physical cores : 6
+# CPU Logical cores  : 12
+# Host memory        : 16468 MB
+# Swap memory        : 1073 MB
+# Total Virtual      : 17542 MB
+# Available Virtual  : 8556 MB
+#-----------------------------------------------------------
+source top_afficheur.tcl -notrace
diff --git a/tp_6/tp_6.runs/synth_1/vivado.pb b/tp_6/tp_6.runs/synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..674b60f3c38993c077ad14ab40dd1e1ee35dd690
Binary files /dev/null and b/tp_6/tp_6.runs/synth_1/vivado.pb differ
diff --git a/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc b/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..311597acfb7c25d35f2c06eaa214f3ba72df52e5
--- /dev/null
+++ b/tp_6/tp_6.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc
@@ -0,0 +1,298 @@
+## This file is a general .xdc for the Basys3 rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+set_property PACKAGE_PIN W5 [get_ports clk]							
+	set_property IOSTANDARD LVCMOS33 [get_ports clk]
+	create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+ 
+set_property PACKAGE_PIN U18 [get_ports reset]
+set_property IOSTANDARD LVCMOS33 [get_ports reset]
+
+## Switches
+set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
+set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
+set_property PACKAGE_PIN W17 [get_ports {sw[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
+set_property PACKAGE_PIN W15 [get_ports {sw[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
+set_property PACKAGE_PIN V15 [get_ports {sw[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
+set_property PACKAGE_PIN W14 [get_ports {sw[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
+set_property PACKAGE_PIN W13 [get_ports {sw[7]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
+set_property PACKAGE_PIN V2 [get_ports {sw[8]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
+set_property PACKAGE_PIN T3 [get_ports {sw[9]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
+set_property PACKAGE_PIN T2 [get_ports {sw[10]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
+set_property PACKAGE_PIN R3 [get_ports {sw[11]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
+set_property PACKAGE_PIN W2 [get_ports {sw[12]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
+set_property PACKAGE_PIN U1 [get_ports {sw[13]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
+set_property PACKAGE_PIN T1 [get_ports {sw[14]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
+set_property PACKAGE_PIN R2 [get_ports {sw[15]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
+ 
+
+## LEDs
+#set_property PACKAGE_PIN U16 [get_ports {led[0]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+#set_property PACKAGE_PIN E19 [get_ports {led[1]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+#set_property PACKAGE_PIN U19 [get_ports {led[2]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+#set_property PACKAGE_PIN V19 [get_ports {led[3]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+#set_property PACKAGE_PIN W18 [get_ports {led[4]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
+#set_property PACKAGE_PIN U15 [get_ports {led[5]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
+#set_property PACKAGE_PIN U14 [get_ports {led[6]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
+#set_property PACKAGE_PIN V14 [get_ports {led[7]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
+#set_property PACKAGE_PIN V13 [get_ports {led[8]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
+#set_property PACKAGE_PIN V3 [get_ports {led[9]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
+#set_property PACKAGE_PIN W3 [get_ports {led[10]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
+#set_property PACKAGE_PIN U3 [get_ports {led[11]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
+#set_property PACKAGE_PIN P3 [get_ports {led[12]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
+#set_property PACKAGE_PIN N3 [get_ports {led[13]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
+#set_property PACKAGE_PIN P1 [get_ports {led[14]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
+#set_property PACKAGE_PIN L1 [get_ports {led[15]}]					
+#	set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
+	
+	
+##7 segment display
+set_property PACKAGE_PIN W7 [get_ports {seg[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
+set_property PACKAGE_PIN W6 [get_ports {seg[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
+set_property PACKAGE_PIN U8 [get_ports {seg[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
+set_property PACKAGE_PIN V8 [get_ports {seg[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
+set_property PACKAGE_PIN U5 [get_ports {seg[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
+set_property PACKAGE_PIN V5 [get_ports {seg[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
+set_property PACKAGE_PIN U7 [get_ports {seg[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
+
+set_property PACKAGE_PIN V7 [get_ports dp]							
+	set_property IOSTANDARD LVCMOS33 [get_ports dp]
+
+set_property PACKAGE_PIN U2 [get_ports {an[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
+set_property PACKAGE_PIN U4 [get_ports {an[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
+set_property PACKAGE_PIN V4 [get_ports {an[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
+set_property PACKAGE_PIN W4 [get_ports {an[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
+
+
+##Buttons
+#set_property PACKAGE_PIN U18 [get_ports btnC]						
+#	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
+#set_property PACKAGE_PIN T18 [get_ports btnU]						
+#	set_property IOSTANDARD LVCMOS33 [get_ports btnU]
+#set_property PACKAGE_PIN W19 [get_ports btnL]						
+#	set_property IOSTANDARD LVCMOS33 [get_ports btnL]
+#set_property PACKAGE_PIN T17 [get_ports btnR]						
+#	set_property IOSTANDARD LVCMOS33 [get_ports btnR]
+#set_property PACKAGE_PIN U17 [get_ports btnD]						
+#	set_property IOSTANDARD LVCMOS33 [get_ports btnD]
+ 
+
+
+##Pmod Header JA
+##Sch name = JA1
+#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
+##Sch name = JA2
+#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
+##Sch name = JA3
+#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
+##Sch name = JA4
+#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
+##Sch name = JA7
+#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
+##Sch name = JA8
+#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
+##Sch name = JA9
+#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
+##Sch name = JA10
+#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
+
+
+
+##Pmod Header JB
+##Sch name = JB1
+#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
+##Sch name = JB2
+#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
+##Sch name = JB3
+#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
+##Sch name = JB4
+#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
+##Sch name = JB7
+#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
+##Sch name = JB8
+#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
+##Sch name = JB9
+#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
+##Sch name = JB10 
+#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
+ 
+
+
+##Pmod Header JC
+##Sch name = JC1
+#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
+##Sch name = JC2
+#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
+##Sch name = JC3
+#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
+##Sch name = JC4
+#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
+##Sch name = JC7
+#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
+##Sch name = JC8
+#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
+##Sch name = JC9
+#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
+##Sch name = JC10
+#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
+
+
+##Pmod Header JXADC
+##Sch name = XA1_P
+#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
+##Sch name = XA2_P
+#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
+##Sch name = XA3_P
+#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
+##Sch name = XA4_P
+#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
+##Sch name = XA1_N
+#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
+##Sch name = XA2_N
+#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
+##Sch name = XA3_N
+#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
+##Sch name = XA4_N
+#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
+
+
+
+##VGA Connector
+#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
+#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
+#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
+#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
+#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
+#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
+#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
+#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
+#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
+#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
+#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
+#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
+#set_property PACKAGE_PIN P19 [get_ports Hsync]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
+#set_property PACKAGE_PIN R19 [get_ports Vsync]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
+
+
+##USB-RS232 Interface
+#set_property PACKAGE_PIN B18 [get_ports RsRx]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
+#set_property PACKAGE_PIN A18 [get_ports RsTx]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
+
+
+##USB HID (PS/2)
+#set_property PACKAGE_PIN C17 [get_ports PS2Clk]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
+	#set_property PULLUP true [get_ports PS2Clk]
+#set_property PACKAGE_PIN B17 [get_ports PS2Data]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]	
+	#set_property PULLUP true [get_ports PS2Data]
+
+
+##Quad SPI Flash
+##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
+##STARTUPE2 primitive.
+#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
+#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
+#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
+#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
+#set_property PACKAGE_PIN K19 [get_ports QspiCSn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
+
diff --git a/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd b/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d82ac16d121ed29c53f29281b5a0fbeb2879811a
--- /dev/null
+++ b/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd
@@ -0,0 +1,73 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 04/22/2025 04:41:36 PM
+-- Design Name: 
+-- Module Name: Enable190 - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+library IEEE; use IEEE.STD_LOGIC_1164.ALL; 
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+use IEEE.STD_LOGIC_unsigned.ALL; 
+
+entity clkdiv is     
+
+Port ( clk : in  STD_LOGIC;            
+       reset : in  STD_LOGIC;            
+       E190, clk190 : out  STD_LOGIC);
+       
+end clkdiv;
+
+architecture clkdiv of clkdiv is
+
+signal clkin: std_logic :='0';
+
+begin     
+
+--clock divider     
+
+    process(clk,reset)     
+    variable q: std_logic_vector(23 downto 0):= X"000000";     
+    begin            
+        
+        if reset ='1' then             
+            q := X"000000";             
+            clkin <= '0';         
+        elsif clk'event and clk = '1' then             
+            q := q+1;             
+        if Q(18)='1' and clkin='0' then    
+            E190 <= '1';
+        else           
+            E190 <= '0';      
+        end if;         
+        
+        end if;         
+        
+        clkin<= Q(18);     
+    
+    end process;     
+    
+    clk190 <= clkin;
+end clkdiv;
+
diff --git a/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd b/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6200209bec22acc236cef0241ae2f024bf645c0f
--- /dev/null
+++ b/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd
@@ -0,0 +1,69 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 04/22/2025 03:05:23 PM
+-- Design Name: 
+-- Module Name: anti_rebond - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity anti_rebond is
+    Port ( inp : in STD_LOGIC;
+           E : in STD_LOGIC;
+           clk : in STD_LOGIC;
+           output : out STD_LOGIC
+           );
+end anti_rebond;
+
+architecture Behavioral of anti_rebond is
+
+-- signaux internes pour connecter les bascules
+signal q_signals : STD_LOGIC_VECTOR(5 downto 0);
+signal o_1 : std_logic;
+
+begin
+     
+    o_1 <= q_signals(0) and q_signals(1) and q_signals(2);
+
+    SYNC : process(clk)
+    begin
+        if (rising_edge(clk)) then
+            if (E = '1') then
+                q_signals(0) <= inp;
+                q_signals(1) <= q_signals(0);
+                q_signals(2) <= q_signals(1);
+            end if;
+                        
+            q_signals(3) <= o_1;
+            q_signals(4) <= q_signals(3);
+            q_signals(5) <= q_signals(4);
+        end if;
+    end process;
+    
+    output <= q_signals(3) and q_signals(4) and (not q_signals(5));   
+    
+end Behavioral;
diff --git a/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd b/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8a8efadaaefef15c27f0ffe7822d35af04afeaad
--- /dev/null
+++ b/tp_6/tp_6.srcs/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd
@@ -0,0 +1,86 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03/11/2025 03:10:55 PM
+-- Design Name: 
+-- Module Name: x7seg - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity x7seg is
+    Port ( sw : in STD_LOGIC_VECTOR (3 downto 0);
+           print : in std_logic_vector(1 downto 0);
+           seg_x7 : out STD_LOGIC_VECTOR (6 downto 0));
+end x7seg;
+
+architecture Behavioral of x7seg is
+
+begin
+    process(sw, print)
+    begin
+--        -- Gestion des cas spécifiques pour Parité et Comparaison
+--        case print is
+--            when "00" =>  -- Parity (Pair)
+--                seg_x7 <= "0001100"; -- Affichage de 'P'
+--            when "01" =>  -- Parity (Impair)
+--                seg_x7 <= "1001111"; -- Affichage de 'I' aligné à gauche
+--            when "10" =>  -- Comp (False)
+--                seg_x7 <= "0001110"; -- Affichage de 'F'
+--            when "11" =>  -- Comp (True)
+--                seg_x7 <= "1110000"; -- Affichage de 't'
+--            when others => 
+--                -- Si print n'est pas utilisé, afficher la valeur de 'sw'
+        case sw is
+            when "0000" =>
+                if print="00" then seg_x7 <= "1000000";
+                else if print ="10" then seg_x7 <= "0000111"; -- Affichage de 't'
+                else if print ="01" then seg_x7 <= "1001111"; end if; --'I'
+                end if; end if;-- 0
+            when "0001" =>
+                if print = "00" then seg_x7 <= "1111001"; -- 1
+                else if print = "10" then seg_x7 <= "0001110"; -- 'F'
+                else if print = "01" then seg_x7 <= "0001100"; end if; -- 'P'
+                end if; end if;
+            when "0010" => if print="00" then seg_x7 <= "0100100"; end if; -- 2
+            when "0011" => if print="00" then seg_x7 <= "0110000"; end if;-- 3
+            when "0100" => if print="00" then seg_x7 <= "0011001"; end if;-- 4
+            when "0101" => if print="00" then seg_x7 <= "0010010"; end if;-- 5
+            when "0110" => if print="00" then seg_x7 <= "0000010"; end if;-- 6
+            when "0111" => if print="00" then seg_x7 <= "1111000"; end if;-- 7
+            when "1000" => if print="00" then seg_x7 <= "0000000"; end if;-- 8
+            when "1001" => if print="00" then seg_x7 <= "0010000"; end if;-- 9
+            when "1010" => if print="00" then seg_x7 <= "0001000"; end if;-- A
+            when "1011" => if print="00" then seg_x7 <= "0000011"; end if;-- b
+            when "1100" => if print="00" then seg_x7 <= "1000110"; end if;-- C
+            when "1101" => if print="00" then seg_x7 <= "0100001"; end if;-- d
+            when "1110" => seg_x7 <= "0000110"; -- E
+            when "1111" => seg_x7 <= "0001110"; -- F
+                        
+            when others => seg_x7 <= "0000000"; -- Ø (Tous les segments allumés)
+        end case;
+    end process;
+end Behavioral;
diff --git a/tp_6/tp_6.srcs/sources_1/new/afficheur_16.vhd b/tp_6/tp_6.srcs/sources_1/new/afficheur_16.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3ba8697bda1e7a7a186d5837c32e54520db80f22
--- /dev/null
+++ b/tp_6/tp_6.srcs/sources_1/new/afficheur_16.vhd
@@ -0,0 +1,97 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity afficheur_16bits is
+    Port (
+        clk190  : in  STD_LOGIC;
+        reset   : in  STD_LOGIC;
+        data    : in  STD_LOGIC_VECTOR(15 downto 0);
+        seg_x7  : out STD_LOGIC_VECTOR(6 downto 0);
+        an      : out STD_LOGIC_VECTOR(3 downto 0)
+    );
+end afficheur_16bits;
+
+architecture Behavioral of afficheur_16bits is
+
+    -- 1. TYPES & ÉTATS
+    type state_type is (st1_digit1, st2_digit2, st3_digit3, st4_digit4);
+    signal state, next_state : state_type;
+
+    -- 2. Signaux internes (sorties de la FSM)
+    signal an_i : STD_LOGIC_VECTOR(3 downto 0);
+    signal sw_i : STD_LOGIC_VECTOR(3 downto 0);
+
+    -- Composant x7seg
+    component x7seg
+        Port (
+            sw : in  STD_LOGIC_VECTOR(3 downto 0);
+            print : in std_logic_vector(1 downto 0);
+            seg_x7 : out STD_LOGIC_VECTOR(6 downto 0)
+        );
+    end component;
+
+begin
+
+    -- 3. SYNCHRONISATION
+    SYNC_PROC : process(clk190)
+    begin
+        if rising_edge(clk190) then
+            if reset = '1' then
+                state <= st1_digit1;
+                an    <= "1110";
+            else
+                state <= next_state;
+                an    <= an_i;
+            end if;
+        end if;
+    end process;
+
+    -- 4. SORTIES (MEALY)
+    OUTPUT_DECODE : process(state, data)
+    begin
+        case state is
+            when st1_digit1 =>
+                sw_i <= data(3 downto 0);
+                an_i <= "1110"; -- activer digit 1
+            when st2_digit2 =>
+                sw_i <= data(7 downto 4);
+                an_i <= "1101"; -- activer digit 2
+            when st3_digit3 =>
+                sw_i <= data(11 downto 8);
+                an_i <= "1011"; -- activer digit 3
+            when st4_digit4 =>
+                sw_i <= data(15 downto 12);
+                an_i <= "0111"; -- activer digit 4
+            when others =>
+                sw_i <= "0000";
+                an_i <= "1111";
+        end case;
+    end process;
+
+    -- 5. TRANSITIONS
+    NEXT_STATE_DECODE : process(state)
+    begin
+        next_state <= state; -- par défaut, rester dans le même état
+        case state is
+            when st1_digit1 =>
+                next_state <= st2_digit2;
+            when st2_digit2 =>
+                next_state <= st3_digit3;
+            when st3_digit3 =>
+                next_state <= st4_digit4;
+            when st4_digit4 =>
+                next_state <= st1_digit1;
+            when others =>
+                next_state <= st1_digit1;
+        end case;
+    end process;
+
+    -- 6. Instanciation du convertisseur 7 segments
+    x7seg_inst : x7seg
+        port map (
+            sw      => sw_i,
+            print   => "00",
+            seg_x7  => seg_x7
+        );
+
+end Behavioral;
diff --git a/tp_6/tp_6.srcs/sources_1/new/top_afficheur.vhd b/tp_6/tp_6.srcs/sources_1/new/top_afficheur.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dd17dcc6570d6674cfb5aacab18d8e5c3d0d50b7
--- /dev/null
+++ b/tp_6/tp_6.srcs/sources_1/new/top_afficheur.vhd
@@ -0,0 +1,58 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity top_afficheur is
+    Port (
+        clk : in std_logic;
+        reset : in std_logic;
+        sw : in std_logic_vector(15 downto 0);
+        seg : out std_logic_vector(6 downto 0);
+        an : out std_logic_vector(3 downto 0)
+    );
+end top_afficheur;
+
+architecture Behavioral of top_afficheur is
+
+    signal clk190 : std_logic;
+    signal E190 : std_logic;
+
+    -- Composants
+    component clkdiv
+        Port (
+            clk : in std_logic;
+            reset : in std_logic;
+            E190 : out std_logic;
+            clk190 : out std_logic
+        );
+    end component;
+
+    component afficheur_16bits
+        Port (
+            clk190 : in STD_LOGIC;
+            data : in STD_LOGIC_VECTOR (15 downto 0);
+            seg_x7 : out STD_LOGIC_VECTOR(6 downto 0);
+            an : out STD_LOGIC_VECTOR(3 downto 0)
+        );
+    end component;
+
+begin
+
+    -- Instance du diviseur de fréquence
+    clkdiv_i : clkdiv
+        port map (
+            clk => clk,
+            reset => reset,
+            E190 => E190,
+            clk190 => clk190
+        );
+
+    -- Instance de l'afficheur 16 bits
+    afficheur : afficheur_16bits
+        port map (
+            clk190 => clk190,
+            data => sw,
+            seg_x7 => seg,
+            an => an
+        );
+
+end Behavioral;
diff --git a/tp_6/tp_6.srcs/sources_1/new/x16seg.v b/tp_6/tp_6.srcs/sources_1/new/x16seg.v
new file mode 100644
index 0000000000000000000000000000000000000000..2df3c656ec0c1af8be0d98f1da67b89052e5fd13
--- /dev/null
+++ b/tp_6/tp_6.srcs/sources_1/new/x16seg.v
@@ -0,0 +1,26 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 29.04.2025 11:09:01
+// Design Name: 
+// Module Name: afficheur_16bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+library IEEE;
+module afficheur_16bits(
+
+    );
+endmodule
diff --git a/tp_6/tp_6.srcs/utils_1/imports/synth_1/top_afficheur.dcp b/tp_6/tp_6.srcs/utils_1/imports/synth_1/top_afficheur.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..bf77ea3abfbb9c5c6d90c73c0b7e427b6d495932
Binary files /dev/null and b/tp_6/tp_6.srcs/utils_1/imports/synth_1/top_afficheur.dcp differ
diff --git a/tp_6/tp_6.xpr b/tp_6/tp_6.xpr
new file mode 100644
index 0000000000000000000000000000000000000000..36ee841390dc419965433181f7c4bdd790720a6b
--- /dev/null
+++ b/tp_6/tp_6.xpr
@@ -0,0 +1,269 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.2 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="68" Path="C:/Users/mamad/INFO/hardware_design/tp_6/tp_6.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="95662433eb29410f954197b62cbba39d"/>
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2024.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2024.1"/>
+    <Option Name="SimulatorVersionQuesta" Val="2024.1"/>
+    <Option Name="SimulatorVersionXcelium" Val="24.03.003"/>
+    <Option Name="SimulatorVersionVCS" Val="V-2023.12-SP1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2024.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="15.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../AppData/Roaming/Xilinx/Vivado/2024.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="basys3"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="UseInlineHdlIP" Val="TRUE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="32">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../tp5_n/tp5_n.srcs/sources_1/new/Enable190.vhd"/>
+          <Attr Name="ImportTime" Val="1745867194"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/afficheur_16.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/imports/hardware_design/tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../tp_3/tp_3.srcs/sources_1/imports/new/x7seg.vhd"/>
+          <Attr Name="ImportTime" Val="1744632998"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/top_afficheur.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/imports/hardware_design/tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="ImportPath" Val="$PPRDIR/../tp5_n/tp5_n.srcs/sources_1/new/anti_rebond.vhd"/>
+          <Attr Name="ImportTime" Val="1745865959"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="top_afficheur"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/constrs_1/imports/Downloads/Basys3_Master.xdc">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../tp5_n/tp5_n.srcs/constrs_1/imports/Downloads/Basys3_Master.xdc"/>
+          <Attr Name="ImportTime" Val="1745865959"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="top_afficheur"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/top_afficheur.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top_afficheur.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 6 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>