From 292106dd6a22282e8df26d02adf0778386ce05c2 Mon Sep 17 00:00:00 2001 From: ahoni <aurelie.saulq@proton.me> Date: Mon, 14 Apr 2025 11:23:26 +0200 Subject: [PATCH] remove print --- .../modules/neurons/BLIF/rblif_parallel.vhd | 11 ++-- .../modules/neurons/SLIF/rslif_parallel.vhd | 12 ++-- .../modules/neurons/SLIF/simplified_lif.vhd | 60 ++++++++++++------- .../neurons/ShiftLif/rshiftlif_parallel.vhd | 12 ++-- .../modules/neurons/ShiftLif/shift_lif.vhd | 57 ++++++++++++------ modneflib/modnef/modnef_torch/model.py | 1 + .../modnef_neurons/slif_model/rslif.py | 8 +-- .../modnef_neurons/slif_model/slif.py | 10 ++-- .../modnef_neurons/srlif_model/shiftlif.py | 2 - 9 files changed, 106 insertions(+), 67 deletions(-) diff --git a/ModNEF_Sources/modules/neurons/BLIF/rblif_parallel.vhd b/ModNEF_Sources/modules/neurons/BLIF/rblif_parallel.vhd index 16f9528..4fdb9c1 100644 --- a/ModNEF_Sources/modules/neurons/BLIF/rblif_parallel.vhd +++ b/ModNEF_Sources/modules/neurons/BLIF/rblif_parallel.vhd @@ -7,7 +7,7 @@ -- Authors : Aurelie Saulquin -- Email : aurelie.saulquin@univ-lille.fr -- --- Version : 1.1.0 +-- Version : 1.1.1 -- Version comment : stable version -- -- Licenses : cern-ohl-s-2.0 @@ -251,7 +251,6 @@ begin if i_start_emu = '1' then tr_fsm_en := '1'; - transmission_neuron_en <= '1'; end if; if rising_edge(i_clk) then @@ -260,8 +259,8 @@ begin start_calc <= '0'; o_emu_busy <= '0'; o_req <= '0'; - rec_ram_en <= '1'; - rec_neuron_en <= '1'; + rec_ram_en <= '0'; + rec_neuron_en <= '0'; rec_spike_flag <= '0'; else case transmission_state is @@ -283,7 +282,7 @@ begin end if; when voltage_update => - transmission_neuron_en <= '0'; + transmission_neuron_en <= '1'; start_calc <= '0'; transmission_state <= check_arbitration; @@ -311,6 +310,7 @@ begin transmission_state <= wait_arbitration; start_arb <= '1'; rec_ram_en <= '1'; + rec_neuron_en <= '1'; rec_spike_flag <= arb_spike_flag; else @@ -331,6 +331,7 @@ begin transmission_state <= idle; o_emu_busy <= '0'; rec_neuron_en <= '0'; + rec_ram_en <= '0'; tr_fsm_en := '0'; end case; end if; diff --git a/ModNEF_Sources/modules/neurons/SLIF/rslif_parallel.vhd b/ModNEF_Sources/modules/neurons/SLIF/rslif_parallel.vhd index 4e18183..894bed2 100644 --- a/ModNEF_Sources/modules/neurons/SLIF/rslif_parallel.vhd +++ b/ModNEF_Sources/modules/neurons/SLIF/rslif_parallel.vhd @@ -7,7 +7,7 @@ -- Authors : Aurelie Saulquin -- Email : aurelie.saulquin@univ-lille.fr -- --- Version : 1.1.0 +-- Version : 1.1.1 -- Version comment : stable version -- -- Licenses : cern-ohl-s-2.0 @@ -240,8 +240,8 @@ begin start_calc <= '0'; o_emu_busy <= '0'; o_req <= '0'; - rec_ram_en <= '1'; - rec_neuron_en <= '1'; + rec_ram_en <= '0'; + rec_neuron_en <= '0'; rec_spike_flag <= '0'; else case transmission_state is @@ -263,7 +263,7 @@ begin end if; when voltage_update => - transmission_neuron_en <= '0'; + transmission_neuron_en <= '1'; start_calc <= '0'; transmission_state <= check_arbitration; @@ -291,6 +291,7 @@ begin transmission_state <= wait_arbitration; start_arb <= '1'; rec_ram_en <= '1'; + rec_neuron_en <= '1'; rec_spike_flag <= arb_spike_flag; else @@ -311,6 +312,7 @@ begin transmission_state <= idle; o_emu_busy <= '0'; rec_neuron_en <= '0'; + rec_ram_en <= '0'; tr_fsm_en := '0'; end case; end if; @@ -338,7 +340,7 @@ begin mem_init_file => mem_init_file_rec ) port map ( i_clk => i_clk, - i_en => '1', + i_en => rec_ram_en, i_addr => output_aer, o_data => rec_data_read ); diff --git a/ModNEF_Sources/modules/neurons/SLIF/simplified_lif.vhd b/ModNEF_Sources/modules/neurons/SLIF/simplified_lif.vhd index 892bcdb..793a13b 100644 --- a/ModNEF_Sources/modules/neurons/SLIF/simplified_lif.vhd +++ b/ModNEF_Sources/modules/neurons/SLIF/simplified_lif.vhd @@ -7,7 +7,7 @@ -- Authors : Aurelie Saulquin -- Email : aurelie.saulquin@univ-lille.fr -- --- Version : 1.2.0 +-- Version : 1.3.0 -- Version comment : stable version -- -- Licenses : cern-ohl-s-2.0 @@ -70,6 +70,8 @@ begin o_spike <= spike; process(i_clk, i_inc_I, i_calc, i_en) + variable I : std_logic_vector(weight_size-1 downto 0); + variable I_rec : std_logic_vector(weight_size-1 downto 0); begin if rising_edge(i_clk) then if i_reset = '1' then @@ -78,14 +80,21 @@ begin if i_en = '1' then if weight_signed then - if spike_flag = '1' or spike_flag_rec = '1' then - if spike_flag = '1' and spike_flag_rec = '0' then - V <= std_logic_vector(signed(V)+signed(weight)); - elsif spike_flag = '0' and spike_flag_rec = '1' then - V <= std_logic_vector(signed(V)+signed(weight_rec)); + if i_inc_I = '1' or i_inc_I_rec = '1' then + + if i_inc_I = '1' then + I := std_logic_vector(signed(i_w)); else - V <= std_logic_vector(signed(V)+signed(weight)+signed(weight_rec)); - end if; + I := (others=>'0'); + end if; + + if i_inc_I_rec = '1' then + I_rec := std_logic_vector(signed(i_w_rec)); + else + I_rec := (others=>'0'); + end if; + + V <= std_logic_vector(signed(V) + signed(I) + signed(I_rec)); elsif i_calc = '1' then if signed(V) >= signed(v_threshold+v_leak) then spike <= '1'; @@ -99,15 +108,24 @@ begin end if; end if; else - if spike_flag = '1' or spike_flag_rec = '1' then - if spike_flag = '1' and spike_flag_rec = '0' then - V <= std_logic_vector(unsigned(V)+unsigned(weight)); - elsif spike_flag = '0' and spike_flag_rec = '1' then - V <= std_logic_vector(unsigned(V)+unsigned(weight_rec)); - else - V <= std_logic_vector(unsigned(V)+unsigned(weight)+unsigned(weight_rec)); - end if; - elsif i_calc = '1' then + if i_inc_I = '1' or i_inc_I_rec = '1' then + + if i_inc_I = '1' then + I := std_logic_vector(unsigned(i_w)); + else + I := (others=>'0'); + end if; + + if i_inc_I_rec = '1' then + I_rec := std_logic_vector(unsigned(i_w_rec)); + else + I_rec := (others=>'0'); + end if; + + V <= std_logic_vector(unsigned(V) + unsigned(I) + unsigned(I_rec)); + + elsif i_calc = '1' then + if unsigned(V) >= unsigned(v_threshold+v_leak) then spike <= '1'; V <= V_rest; @@ -121,10 +139,10 @@ begin end if; end if; - spike_flag <= i_inc_I; - weight <= i_w; - spike_flag_rec <= i_inc_I_rec; - weight_rec <= i_w_rec; + -- spike_flag <= i_inc_I; + -- weight <= i_w; + -- spike_flag_rec <= i_inc_I_rec; + -- weight_rec <= i_w_rec; end if; end if; diff --git a/ModNEF_Sources/modules/neurons/ShiftLif/rshiftlif_parallel.vhd b/ModNEF_Sources/modules/neurons/ShiftLif/rshiftlif_parallel.vhd index 1af3b8a..8d3d6ad 100644 --- a/ModNEF_Sources/modules/neurons/ShiftLif/rshiftlif_parallel.vhd +++ b/ModNEF_Sources/modules/neurons/ShiftLif/rshiftlif_parallel.vhd @@ -7,7 +7,7 @@ -- Authors : Aurelie Saulquin -- Email : aurelie.saulquin@univ-lille.fr -- --- Version : 1.1.0 +-- Version : 1.1.1 -- Version comment : stable version -- -- Licenses : cern-ohl-s-2.0 @@ -237,8 +237,8 @@ begin start_calc <= '0'; o_emu_busy <= '0'; o_req <= '0'; - rec_ram_en <= '1'; - rec_neuron_en <= '1'; + rec_ram_en <= '0'; + rec_neuron_en <= '0'; rec_spike_flag <= '0'; else case transmission_state is @@ -260,7 +260,7 @@ begin end if; when voltage_update => - transmission_neuron_en <= '0'; + transmission_neuron_en <= '1'; start_calc <= '0'; transmission_state <= check_arbitration; @@ -288,6 +288,7 @@ begin transmission_state <= wait_arbitration; start_arb <= '1'; rec_ram_en <= '1'; + rec_neuron_en <= '1'; rec_spike_flag <= arb_spike_flag; else @@ -308,6 +309,7 @@ begin transmission_state <= idle; o_emu_busy <= '0'; rec_neuron_en <= '0'; + rec_ram_en <= '0'; tr_fsm_en := '0'; end case; end if; @@ -335,7 +337,7 @@ begin mem_init_file => mem_init_file_rec ) port map ( i_clk => i_clk, - i_en => '1', + i_en => rec_ram_en, i_addr => output_aer, o_data => rec_data_read ); diff --git a/ModNEF_Sources/modules/neurons/ShiftLif/shift_lif.vhd b/ModNEF_Sources/modules/neurons/ShiftLif/shift_lif.vhd index 84e97fa..9f6b460 100644 --- a/ModNEF_Sources/modules/neurons/ShiftLif/shift_lif.vhd +++ b/ModNEF_Sources/modules/neurons/ShiftLif/shift_lif.vhd @@ -7,7 +7,7 @@ -- Authors : Aurelie Saulquin -- Email : aurelie.saulquin@univ-lille.fr -- --- Version : 1.1.0 +-- Version : 1.2.0 -- Version comment : stable version -- -- Licenses : cern-ohl-s-2.0 @@ -69,6 +69,9 @@ begin o_spike <= spike; process(i_clk, i_inc_I, i_calc, i_en) + variable I : std_logic_vector(weight_size-1 downto 0); + variable I_rec : std_logic_vector(weight_size-1 downto 0); + variable v_buff : std_logic_vector(variable_size-1 downto 0); begin if rising_edge(i_clk) then if i_reset = '1' then @@ -77,46 +80,62 @@ begin if i_en = '1' then if weight_signed then - if spike_flag = '1' or spike_flag_rec = '1' then - if spike_flag = '1' and spike_flag_rec = '0' then - V <= std_logic_vector(signed(V) + signed(weight)); - elsif spike_flag = '0' and spike_flag_rec = '1' then - V <= std_logic_vector(signed(V) + signed(weight_rec)); + if i_inc_I = '1' or i_inc_I_rec = '1' then + + if i_inc_I = '1' then + I := std_logic_vector(signed(i_w)); else - V <= std_logic_vector(signed(V) + signed(weight) + signed(weight_rec)); + I := (others=>'0'); end if; + + if i_inc_I_rec = '1' then + I_rec := std_logic_vector(signed(i_w_rec)); + else + I_rec := (others=>'0'); + end if; + + V <= std_logic_vector(signed(V) + signed(I) + signed(I_rec)); elsif i_calc='1' then - if signed(V) >= signed(v_threshold) then + V_buff := std_logic_vector(signed(V)-signed(shift_right(signed(V), shift))); + if signed(V_buff) >= signed(v_threshold) then spike <= '1'; if reset = "zero" then V <= (others=>'0'); else - V <= std_logic_vector(signed(V) - signed(v_threshold)); + V <= std_logic_vector(signed(V_buff) - signed(v_threshold)); end if; else - V <= std_logic_vector(signed(V)-signed(shift_right(signed(V), shift))); + V <= V_buff; spike <= '0'; end if; end if; else - if spike_flag = '1' or spike_flag_rec = '1' then - if spike_flag = '1' and spike_flag_rec = '0' then - V <= std_logic_vector(unsigned(V) + unsigned(weight)); - elsif spike_flag = '0' and spike_flag_rec = '1' then - V <= std_logic_vector(unsigned(V) + unsigned(weight_rec)); + if i_inc_I = '1' or i_inc_I_rec = '1' then + + if i_inc_I = '1' then + I := std_logic_vector(unsigned(i_w)); else - V <= std_logic_vector(unsigned(V) + unsigned(weight) + unsigned(weight_rec)); + I := (others=>'0'); end if; + + if i_inc_I_rec = '1' then + I_rec := std_logic_vector(unsigned(i_w_rec)); + else + I_rec := (others=>'0'); + end if; + + V <= std_logic_vector(unsigned(V) + unsigned(I) + unsigned(I_rec)); elsif i_calc='1' then - if unsigned(V) >= unsigned(v_threshold) then + V_buff := std_logic_vector(unsigned(V)-unsigned(shift_right(unsigned(V), shift))); + if unsigned(V_buff) >= unsigned(v_threshold) then spike <= '1'; if reset = "zero" then V <= (others=>'0'); else - V <= std_logic_vector(unsigned(V) - unsigned(v_threshold)); + V <= std_logic_vector(unsigned(V_buff) - unsigned(v_threshold)); end if; else - V <= std_logic_vector(unsigned(V)-unsigned(shift_right(unsigned(V), shift))); + V <= V_buff; spike <= '0'; end if; end if; diff --git a/modneflib/modnef/modnef_torch/model.py b/modneflib/modnef/modnef_torch/model.py index 84146c6..f63da28 100644 --- a/modneflib/modnef/modnef_torch/model.py +++ b/modneflib/modnef/modnef_torch/model.py @@ -198,6 +198,7 @@ class ModNEFModel(nn.Module): if self.driver != None: self.driver.close() + self.driver = None def forward(self, input_spikes): """ diff --git a/modneflib/modnef/modnef_torch/modnef_neurons/slif_model/rslif.py b/modneflib/modnef/modnef_torch/modnef_neurons/slif_model/rslif.py index a2ab9a4..895adce 100644 --- a/modneflib/modnef/modnef_torch/modnef_neurons/slif_model/rslif.py +++ b/modneflib/modnef/modnef_torch/modnef_neurons/slif_model/rslif.py @@ -325,10 +325,10 @@ class RSLIF(ModNEFNeuron): We assume you've already intialize quantizer """ - self.v_leak.data = QuantizeSTE(self.v_leak, self.quantizer) - self.v_min.data = QuantizeSTE(self.v_min, self.quantizer) - self.v_rest.data = QuantizeSTE(self.v_rest, self.quantizer) - self.threshold.data = QuantizeSTE(self.threshold, self.quantizer) + self.v_leak.data = QuantizeSTE.apply(self.v_leak, self.quantizer) + self.v_min.data = QuantizeSTE.apply(self.v_min, self.quantizer) + self.v_rest.data = QuantizeSTE.apply(self.v_rest, self.quantizer) + self.threshold.data = QuantizeSTE.apply(self.threshold, self.quantizer) @classmethod def detach_hidden(cls): diff --git a/modneflib/modnef/modnef_torch/modnef_neurons/slif_model/slif.py b/modneflib/modnef/modnef_torch/modnef_neurons/slif_model/slif.py index 2ee8653..5e93c39 100644 --- a/modneflib/modnef/modnef_torch/modnef_neurons/slif_model/slif.py +++ b/modneflib/modnef/modnef_torch/modnef_neurons/slif_model/slif.py @@ -282,9 +282,7 @@ class SLIF(ModNEFNeuron): if self.hardware_description["variable_size"]==-1: if self.hardware_estimation_flag: val_max = max(abs(self.val_max), abs(self.val_min)) - print(val_max) val_max = self.quantizer(val_max) - print(val_max) self.hardware_description["variable_size"] = ceil(log(val_max)/log(256))*8 else: self.hardware_description["variable_size"]=16 @@ -316,10 +314,10 @@ class SLIF(ModNEFNeuron): We assume you've already intialize quantizer """ - self.v_leak.data = QuantizeSTE(self.v_leak, self.quantizer) - self.v_min.data = QuantizeSTE(self.v_min, self.quantizer) - self.v_rest.data = QuantizeSTE(self.v_rest, self.quantizer) - self.threshold.data = QuantizeSTE(self.threshold, self.quantizer) + self.v_leak.data = QuantizeSTE.apply(self.v_leak, self.quantizer) + self.v_min.data = QuantizeSTE.apply(self.v_min, self.quantizer) + self.v_rest.data = QuantizeSTE.apply(self.v_rest, self.quantizer) + self.threshold.data = QuantizeSTE.apply(self.threshold, self.quantizer) @classmethod def detach_hidden(cls): diff --git a/modneflib/modnef/modnef_torch/modnef_neurons/srlif_model/shiftlif.py b/modneflib/modnef/modnef_torch/modnef_neurons/srlif_model/shiftlif.py index e2cb265..92698f8 100644 --- a/modneflib/modnef/modnef_torch/modnef_neurons/srlif_model/shiftlif.py +++ b/modneflib/modnef/modnef_torch/modnef_neurons/srlif_model/shiftlif.py @@ -140,8 +140,6 @@ class ShiftLIF(ModNEFNeuron): "variable_size" : -1 } - print(threshold) - @classmethod def from_dict(cls, dict, spike_grad): """ -- GitLab